Add selectors for cell type properties

kernel/register.cc

@@ -1074,6 +1074,36 @@ struct HelpPass : public Pass {
 				log("\n");
 				return;
 			}
+			else if (args[1] == "-celltypes") {
+				log("\n");
+				for (auto &it : cell_help_messages.cell_help) {
+					SimHelper help_cell = it.second;
+					auto *ct = yosys_celltypes.get_cell(it.first);
+					char ct_flags[8] = "";
+					if (ct != nullptr && ct->is_internal) {
+						ct_flags[0] = ct->is_evaluable ? 'E' : '-';
+						ct_flags[1] = ct->is_combinatorial ? 'C' : '-';
+						ct_flags[2] = ct->is_synthesizable ? 'S' : '-';
+						ct_flags[3] = ct->is_builtin_ff ? 'M' : '-';
+						ct_flags[4] = ct->is_formal ? 'F' : '-';
+						ct_flags[5] = ct->is_metainfo ? 'I' : '-';
+						ct_flags[6] = ct->has_effects ? 'X' : '-';
+						ct_flags[7] = 0;
+					}
+					log("    %-15s %s\n", help_cell.name.c_str(), ct_flags);
+				}
+				log("\n");
+				log("Legend:\n");
+				log("    E = evaluable\n");
+				log("    C = combinatorial\n");
+				log("    S = synthesizable\n");
+				log("    M = builtin_ff\n");
+				log("    F = formal\n");
+				log("    I = metainfo\n");
+				log("    X = effects\n");
+				log("\n");
+				return;
+			}
 			// this option is undocumented as it is for internal use only
 			else if (args[1] == "-write-rst-command-reference-manual") {
 				for (auto &it : pass_register) {

kernel/rtlil.cc

@@ -4063,9 +4063,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 			type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
 		return;
 
-	if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux)) {
+	if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) {
 		parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
-		if (type != ID($buf) && type != ID($mux))
+		if (type.in(ID($pmux), ID($bmux)))
 			parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
 		check();
 		return;
@@ -4115,7 +4115,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
 	}
 
-	if (connections_.count(ID::Y))
+	if (connections_.count(ID::Y) && type != ID($concat))
 		parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
 
 	if (connections_.count(ID::Q))

passes/cmds/select.cc

@@ -141,6 +141,39 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, co
 	return match_attr(attributes, match_expr, std::string(), 0);
 }
 
+static bool match_type_prop(RTLIL::IdString type, const std::string &property)
+{
+	auto *ct = yosys_celltypes.get_cell(type);
+	if (ct == nullptr) {
+		return false;
+	} else
+	if (property.compare("internal") == 0) {
+		return ct->is_internal;
+	} else
+	if (property.compare("evaluable") == 0) {
+		return ct->is_evaluable;
+	} else
+	if (property.compare("combinatorial") == 0) {
+		return ct->is_combinatorial;
+	} else
+	if (property.compare("synthesizable") == 0) {
+		return ct->is_synthesizable;
+	} else
+	if (property.compare("builtin_ff") == 0) {
+		return ct->is_builtin_ff;
+	} else
+	if (property.compare("formal") == 0) {
+		return ct->is_formal;
+	} else
+	if (property.compare("metainfo") == 0) {
+		return ct->is_metainfo;
+	} else
+	if (property.compare("effects") == 0) {
+		return ct->has_effects;
+	} else
+		log_cmd_error("Unsupported type property '%s'!\n", property.c_str());
+}
+
 static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 {
 	if (lhs.full_selection) {
@@ -891,6 +924,11 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 						sel.selected_members[mod->name].insert(cell->name);
 			}
 		} else
+		if (arg_memb.compare(0, 2, "y:") == 0) {
+			for (auto cell : mod->cells())
+				if (match_type_prop(cell->type, arg_memb.substr(2)))
+					sel.selected_members[mod->name].insert(cell->name);
+		} else
 		if (arg_memb.compare(0, 2, "p:") == 0) {
 			for (auto &it : mod->processes)
 				if (match_ids(it.first, arg_memb.substr(2)))
@@ -1178,6 +1216,11 @@ struct SelectPass : public Pass {
 		log("    t:@<name>\n");
 		log("        all cells with a type matching a module in the saved selection <name>\n");
 		log("\n");
+		log("    y:<property>\n");
+		log("        all cells with a given type property, possible values are:\n");
+		log("        evaluable, combinatorial, synthesizable, builtin_ff, formal\n");
+		log("        (currently only internal cells can have type properties)\n");
+		log("\n");
 		log("    p:<pattern>\n");
 		log("        all processes with a name matching the given pattern\n");
 		log("\n");