Variable vector indices in Verilog

[CatalpaEel]

Emm, is yosys unable to handle this syntax? The JSON produce a cell of type "shiftx".

module top_module (
        input [3:0] a,
        input [1:0] x,
        output z);
    assign z = a[x];
endmodule

JSON:

"cells": {
  "$shiftx${workspace}/demo.v:0$1": {
    "hide_name": 1,
    "type": "$shiftx",
    "parameters": {
      "A_SIGNED": "00000000000000000000000000000000",
      "A_WIDTH": "00000000000000000000000000000100",
      "B_SIGNED": "00000000000000000000000000000000",
      "B_WIDTH": "00000000000000000000000000000010",
      "Y_WIDTH": "00000000000000000000000000000001"
    },
    "attributes": {
      "src": "{workspace}/demo.v:0.0-0.0"
    },
    "port_directions": {
      "A": "input",
      "B": "input",
      "Y": "output"
    },
    "connections": {
      "A": [ 2, 3, 4, 5 ],
      "B": [ 6, 7 ],
      "Y": [ 8 ]
    }
  }
},

[povik]

That looks to be the expected output and Yosys should handle this syntax. What makes you think otherwise?

[CatalpaEel]

Because it gets stuck when generating netlist, and I am confused by the name "shiftx".

[povik]

You can look up the name shiftx in the documentation. You'll need to provide more details about the netlist generation getting stuck (ideally a reproducer) to receive help.

[CatalpaEel]

Oh thank you very much, this is a issue of another software. Sorry to bother you.