Update docs for VSRC_LOC_FILES, re-enable running IR drop without it

docs/source/reference/configuration.md

@@ -78,7 +78,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 |-|-|
 | `SYNTH_AUTONAME` <a id="SYNTH_AUTONAME"></a> | Add a synthesis step to generate names for instances. This results in instance names that can be very long, but may be more useful than the internal names that are six digit numbers. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
 | `SYNTH_BIN` <a id="SYNTH_BIN"></a> | The yosys binary used in the flow. <br> (Default: `yosys`) |
-| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: NONE) |
+| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: None) |
 | `SYNTH_CLOCK_UNCERTAINTY` <a id="SYNTH_CLOCK_UNCERTAINTY"></a>  | Specifies a value for the clock uncertainty/jitter for timing analysis. <br> (Default: `0.25`) |
 | `SYNTH_CLOCK_TRANSITION` <a id="SYNTH_CLOCK_TRANSITION"></a>  |  Specifies a value for the clock transition /slew for timing analysis. <br> (Default: `0.15`) |
 | `SYNTH_TIMING_DERATE` <a id="SYNTH_TIMING_DERATE"></a>  | Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing. <br> (Default: `+5%/-5%`) |
@@ -107,7 +107,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | Variable | Description |
 |-|-|
 | `STA_REPORT_POWER` <a id="STA_REPORT_POWER"></a> | Enables reporting power in sta. <br> (Default: `1`) |
-| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files.  <br> (Default: NONE) |
+| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files.  <br> (Default: None) |
 | `STA_WRITE_LIB` <a id="STA_WRITE_LIB"></a> | Controls whether a timing model is written using OpenROAD OpenSTA after static timing analysis. This is an option as it in its current state, the timing model generation (and the model itself) can be quite buggy. <br> (Default: `1`) |
 
 ## Floorplanning (FP)
@@ -149,15 +149,15 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `FP_PDN_HORIZONTAL_HALO` <a id="FP_PDN_HORIZONTAL_HALO"></a> | Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: `10`) |
 | `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: set to the value of `FP_PDN_HORIZONTAL_HALO`) |
 | `FP_PDN_FULL_STACK` <a id="FP_PDN_FULL_STACK"></a> | Controls the layers used in the power grid. If set to `0` (Tcl)/`false` (JSON), only the lower, vertical layer will be used, which is useful when hardening a macro for integrating into a larger top-level design. <br> (Default: `1`)|
-| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: NONE)|
-| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
-| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
+| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: None)|
+| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
+| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
 | `FP_DEF_TEMPLATE` <a id="FP_DEF_TEMPLATE"></a> | Points to the DEF file to be used as a template when running `apply_def_template`. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the `CURRENT_DEF`. |
 | `VDD_NETS` <a id="VDD_NETS"></a> | Specifies the power nets/pins to be used when creating the power grid for the design. |
 | `GND_NETS` <a id="GND_NETS"></a> | Specifies the ground nets/pins to be used when creating the power grid for the design. |
 | `SYNTH_USE_PG_PINS_DEFINES` <a id="SYNTH_USE_PG_PINS_DEFINES"></a> | Specifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract `VDD_NETS` and `GND_NET` variables from the verilog, with the assumption that they will be order `inout vdd1, inout gnd1, inout vdd2, inout gnd2, ...`. |
 | `FP_IO_MIN_DISTANCE` <a id="FP_IO_MIN_DISTANCE"></a>  | The minmimum distance between the IOs in microns. <br> (Default: `3`) |
-| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a>  | A configuration file passed to padringer, a padframe generator. <br> (Default: NONE) |
+| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a>  | A configuration file passed to padringer, a padframe generator. <br> (Default: None) |
 | `PDN_CFG` <a id="PDN_CFG"></a> | **Deprecated: Use `FP_PDN_CFG`**: Points to a PDN configuration file that describes how to construct the PDN in detail. |
 | `FP_HORIZONTAL_HALO` <a id="FP_HORIZONTAL_HALO"></a> | **Deprecated: Use `FP_PDN_HORIZONTAL_HALO`**: Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns.|
 | `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | **Deprecated: Use `FP_PDN_VERTICAL_HALO`**: Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. |
@@ -315,7 +315,7 @@ These variables worked initially, but they were too sky130 specific and will be
 |Variable|Description|
 |-|-|
 | `RUN_IRDROP_REPORT` <a id="RUN_IRDROP_REPORT"></a> | Creates an IR Drop report using OpenROAD PSM. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
-| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | PSM loc file for power and ground nets. Variable should be provided as a json/tcl list or a space delimited tcl string as follows: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info.<br> (Default: NONE)  |
+| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | Map of voltage source nets to OpenROAD PSM location files. Variable should be provided as a Tcl dict, i.e.: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info. <br> (Default: None)  |
 
 ## Signoff
 

scripts/openroad/irdrop.tcl

@@ -26,12 +26,19 @@ if { [info exists ::env(VSRC_LOC_FILES)] } {
         analyze_power_grid {*}$arg_list
     }
 } else {
-    foreach net "$::env(VDD_NETS) $::env(GND_NETS)" {
+    foreach net "$::env(VDD_NETS)" {
         set arg_list [list]
         lappend arg_list -net $net
         lappend arg_list -outfile $::env(_tmp_save_rpt_prefix)-$net.rpt
         analyze_power_grid {*}$arg_list
     }
+    foreach net "$::env(GND_NETS)" {
+        set arg_list [list]
+        lappend arg_list -net $net
+        lappend arg_list -outfile $::env(_tmp_save_rpt_prefix)-$net.rpt
+        set_pdnsim_net_voltage -net $net -voltage 0
+        analyze_power_grid {*}$arg_list
+    }
 }
 
 

scripts/tcl_commands/all.tcl

@@ -1230,8 +1230,7 @@ proc run_antenna_check {args} {
 
 proc run_irdrop_report {args} {
     if { ![info exists ::env(VSRC_LOC_FILES)] } {
-        puts_warn "Skipping IR-drop analysis as VSRC_LOC_FILES was not given a value. If you are not integrating a top-level chip for manufacture, you can ignore this warning, otherwise, see the documentation for VSRC_LOC_FILES."
-        return
+        puts_warn "VSRC_LOC_FILES was not given a value, which may make the results of IR drop analysis inaccurate. If you are not integrating a top-level chip for manufacture, you may ignore this warning, otherwise, see the documentation for VSRC_LOC_FILES."
     }
 
     increment_index