fix: correct PTE flags for LoongArch64 and correct TLB flush mask for aarch64

[mingzi47]

LoongArch

After remove W flag, page_fault is not triggered when a page is modified

In page_table_multiarch, the D flag is added to set_flags by default, so page_fault cannot be triggered

LoongArch Doc

Page modify exception: This exception is triggered when the virtual address of the store operation finds a match in the TLB with V=1 and privilege level is legal and D=0.

AArch64

This code is taken from the arm documentation

STR  X1, [X5]        // Write to translation table entry
DSB  ISH             // Barrier instructions - not covered in this guide
TLBI VAAE1IS  , X0   // Invalidate VA specified by X0, in EL0/1
                     // virtual address space for all ASIDs
DSB  ISH             // Barrier instructions - not covered in this guide
ISB                  // Synchronize context on this processor

The description of the X0 register D8.17.5.1.

For TLB maintenance instructions that take a VA, an ASID, or both as an argument,
and that do not apply to a range of addresses, the register specified by the Xt
argument has the following format:

• Register bits[63:48] are one of the following:
  • If the instruction requires an ASID argument, the ASID.
  • If the instruction does not require an ASID argument, RES0.
• If FEAT_TTL is not implemented, then register bits[47:44] are RES0.
• If FEAT_TTL is implemented, then register bits[47:44] are one of the following:
  • If the instruction requires a VA argument, the translation table level hint, TTL.
  • If the instruction does not require a VA argument, RES0.
• Register bits[43:0] are one of the following:
  • If the instruction requires a VA argument, VA[55:12].
  • If the instruction does not require a VA argument, RES0.

Relate

oscomp/arceos#50 (comment)

[AsakuraMizu]

@mingzi47 First of all, thanks for your contributions! I'm now looking to upstream this fork to the original repository. Would you be open to porting the this PR to https://github.com/arceos-org/page_table_multiarch? If you're unavailable, I'd be happy to help port it.

[mingzi47]

@AsakuraMizu I might have time to work on this as early as next week.

If you want it to be done sooner, I’d really appreciate your help in getting it finished. Thank you!

[AsakuraMizu]

If you want it to be done sooner, I’d really appreciate your help in getting it finished. Thank you!

I've split the fix for AArch64, but I left the LoongArch part alone because both this PR and #1 use the D bit and I'm not sure about the correctness and possible conflicts.

[mingzi47]

This PR aims to fix the issue where, regardless of the MappingFlags, the PTEFlags would always include the D flag (even if the mapping is read-only, the D flag would still be present).

https://elixir.bootlin.com/linux/v6.15.3/source/arch/loongarch/include/asm/pgtable.h#L394

but I left the LoongArch part alone because both this PR and #1 use the D bit and I'm not sure about the correctness and possible conflicts.

I believe there should be no conflict, but you can confirm the author of it.

Thanks again for port it.