Move the DSv4 MI355X SGLang AgentX arm to sgl-dev v0.5.18 and split TP4/TP8 by concurrency - #2710
Move the DSv4 MI355X SGLang AgentX arm to sgl-dev v0.5.18 and split TP4/TP8 by concurrency#2710karverma-amd wants to merge 4 commits into
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Ports the image and serving flags validated on the AMD fork onto this key. Runner and search space are unchanged. - image: lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260813 -> rocm/sgl-dev:v0.5.18-rocm720-mi35x-20260822 - enable the DSv4 kernel fusions the new image carries, all default off in environ.py: SGLANG_OPT_USE_AITER_BATCHED_GEMM, SGLANG_OPT_NATIVE_BPRESHUFFLE_SCALE and SGLANG_OPT_FUSE_COMPRESS_NORM_ROPE - mem-fraction-static 0.85 -> 0.89 to enlarge the full-attention KV pool, keeping enough remainder for the compressor state pools that are allocated after it - --disable-shared-experts-fusion -> --enforce-shared-experts-fusion; the tuned MoE tables in this image cover the resulting (inter_dim 384, expert 385, topk 7) shape at the token sizes this workload hits The stale comment claiming the image matches the disagg AgentX entry is updated; that key is still on v0.5.17-20260817. Co-authored-by: Cursor <cursoragent@cursor.com>
TP4 owns the low-concurrency end at [1, 2, 4, 8, 10] with no host KV tier, where halving the GPUs per replica raises throughput per GPU. The TP8 no-offload arm drops from [1, 2, 4, 8, 16] to [16], so TP8 picks up where TP4 leaves off instead of duplicating those points. conc 16 still appears on both TP8 arms to isolate the host KV tier's gain. This removes the published TP8 concurrency 1, 2, 4 and 8 points and adds TP4 concurrency 1, 2, 4, 8 and 10. TP4 doubles per-rank weights and leaves far less room for KV, which is why it stops at concurrency 10 and ships no hicache variant. The comment's "pure TP8 only" phrasing is updated to "tensor-parallel only", which is what it meant - the exclusion is DP-attention, not TP4. Co-authored-by: Cursor <cursoragent@cursor.com>
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Co-authored-by: Cursor <cursoragent@cursor.com>
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| # DSv4 kernel fusions carried by the sgl-dev image: aiter batched GEMM for the | ||
| # absorbed MLA projections, native b-preshuffle scale handling, and a fused | ||
| # compress+norm+rope epilogue. All three default off in environ.py. | ||
| export SGLANG_OPT_USE_AITER_BATCHED_GEMM=1 |
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Missing aiter master switch
Medium Severity
SGLANG_OPT_USE_AITER_BATCHED_GEMM is enabled to route the DSv4 MLA absorb GEMM through aiter, but SGLANG_USE_AITER is never set. Sibling MI355X recipes and the multi-node DSv4 env export that master switch; without it the batched-GEMM path typically stays inactive, so the advertised fusion does not take effect.
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1am9trash
added
AMD
full-sweep-enabled
agentx
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Dispatched trusted sweep run for approved external revision 已为获批的外部提交 |
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Sglang cookbook update PR for inferneceX is ready. |
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/reuse-sweep-run 32626907474 |
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As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. https://inferencex.semianalysis.com/inference?unofficialRun=32626907474
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. https://inferencex.semianalysis.com/evaluation?unofficialRun=32626907474
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
- Verified against the current MODELS.md that this PR does not submit a deprecated model, scenario, or model-scenario combination.
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that every single-node vLLM/SGLang recipe in this PR is documented in the official vLLM recipes and/or the SGLang cookbook:
- I linked the corresponding upstream PR in the vLLM recipe repo or SGLang repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
- Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/
<PR_NUMBER>.md— named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section. - If this PR uses
append-only: true, verified that it only adds generated points or recipe variants inside a selected existing config/scenario and existing same-image visual curve: every previously generated point remains present with the same recipe, no prior point is removed or rerun, and every benchmark-affecting change in the complete diff can affect only the corresponding newly appended points (never an existing point), regardless of which file contains it. - If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
Additional detail section:
- Cookbook PR (merged): https://docs.sglang.io/cookbook/autoregressive/DeepSeek/DeepSeek-V4
Signed: @1am9trash
❌❌❌ REJECTED ❌❌❌@1am9trash — three blockers: no passing sweep/eval is anchored to any commit in this PR (the trusted external e2e run is not consumable by ✅ Check 0 (CODEOWNER): PASS — @1am9trash is a listed owner of |
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Reviewed by Cursor Bugbot for commit 4a1f75d. Configure here.
| # tier. | ||
| dsv4-fp4-mi355x-sglang-agentic-mtp: | ||
| image: lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260813 | ||
| image: lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260822 |
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Invented nonexistent image tag
High Severity
The image was rewritten from the validated rocm/sgl-dev:v0.5.18-rocm720-mi35x-20260822 to lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260822. That lmsysorg tag does not appear on Docker Hub (recent v0.5.17 MI35x nightlies stop around 20260819; no v0.5.18 lmsysorg tags yet), so pulls will fail. The date looks carried over from the sgl-dev tag while org and version were changed. The recipe still enables DSv4 fusions and --enforce-shared-experts-fusion that this PR tied to the sgl-dev v0.5.18 image.
Reviewed by Cursor Bugbot for commit 4a1f75d. Configure here.
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Superseded by #2713, which is branched directly on the repo rather than a fork, and carries the corrected image (lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260822) with only SGLANG_OPT_USE_AITER_BATCHED_GEMM enabled. |
3 participants
Summary
Updates
dsv4-fp4-mi355x-sglang-agentic-mtpto the image and serving flags validated on the AMD fork, and splits the search space so TP4 covers the low-concurrency end.Image and serving flags (
a3feffec)lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260813→rocm/sgl-dev:v0.5.18-rocm720-mi35x-20260822environ.py:SGLANG_OPT_USE_AITER_BATCHED_GEMM,SGLANG_OPT_NATIVE_BPRESHUFFLE_SCALE,SGLANG_OPT_FUSE_COMPRESS_NORM_ROPEmem-fraction-static0.85 → 0.89, enlarging the full-attention KV pool. The DSv4 compressor state pools are sized from that pool and allocated after it, outside this budget, so the remainder still has to cover them — which is why this stops short of 0.90.--disable-shared-experts-fusion→--enforce-shared-experts-fusion. The tuned MoE tables in this image cover the resulting(inter_dim 384, expert 385, topk 7)shape at the token sizes this workload hits; on the previous image that shape fell back to a heuristic FlyDSL kernel.Search space (
5823400)[1, 2, 4, 8, 10]with no host KV tier, where halving the GPUs per replica raises throughput per GPU[1, 2, 4, 8, 16]to[16], so TP8 picks up where TP4 leaves off rather than duplicating those points[16, 32, 48], and concurrency 16 still appears on both TP8 arms to isolate the host KV tier's gain.TP4 doubles per-rank weights and leaves far less room for KV, which is why it stops at concurrency 10 and ships no hicache variant.
The
runner(cluster:mi355x-amds) is unchanged, and no directory structure changed.Also corrects a comment that claimed the image matched the disagg AgentX entry — that key is still on
v0.5.17-...-20260817— and rewords "pure TP8 only" to "tensor-parallel only", which is what it meant: the exclusion is DP-attention, not TP4.Test plan
bash -n benchmarks/single_node/agentic/dsv4_fp4_mi355x_sglang_mtp.shconfigs/amd-master.yamlandperf-changelog.yamlboth parseprocess_changelog.py --base-ref main --head-ref HEADtriggers all 9 cells plus the conc-48 agentic evalMade with Cursor