[bsp][rockchip][rk2108]: add rk2108 base support.

bsp/rockchip/common/.ignore_format.yml

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+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- rk_hal

bsp/rockchip/common/HalSConscript

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+import rtconfig
+Import('RTT_ROOT')
+Import('SOC')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+hal_lib = cwd + '/rk_hal/lib'
+
+# The set of source files associated with this SConscript file.
+src = Glob(hal_lib + '/CMSIS/Device/' + SOC + '/Source/*.c')
+src += Glob(hal_lib + '/hal/src/*.c')
+src += Glob(hal_lib + '/hal/src/*/*.c')
+src += Glob(hal_lib + '/bsp/' + SOC + '/*.c')
+
+#add include path
+path = [hal_lib + '/hal/inc',
+        hal_lib + '/bsp/' + SOC,
+        hal_lib + '/CMSIS/Device/' + SOC + '/Include',
+        hal_lib + '/CMSIS/Core/Include']
+
+group = DefineGroup(SOC + '_StdPeriph', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/rockchip/common/drivers/Kconfig

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+menu "RT-Thread rockchip common drivers"
+
+config RT_USING_RESET
+    bool "Enable reset support"
+
+config RT_USING_CACHE
+    bool "Enable cache"
+    default y
+
+config RT_USING_UNCACHE_HEAP
+    bool "Enable uncache heap"
+    select RT_USING_MEMHEAP
+    default n
+
+    if RT_USING_UNCACHE_HEAP && ARCH_ARM_CORTEX_M
+    config RT_UNCACHE_HEAP_ORDER
+        hex "For MCU uncache heap size(0x0D=16KB, 0x0E=32KB, 0x0F=64KB)"
+        range 0x0D 0x10
+        depends on RT_USING_UNCACHE_HEAP
+        default 0x0E
+        help
+            set uncache heap size, it in tail of sram
+            Examples:
+                0x0D   =>   16KB
+                0x0E   =>   32KB
+                0x0F   =>   64KB
+                0x10   =>   128KB
+    endif
+
+config RT_USING_LARGE_HEAP
+    bool "Enable large heap"
+    select RT_USING_MEMHEAP
+    default n
+
+    if RT_USING_LARGE_HEAP
+    config RT_LARGE_MALLOC_THRRESH
+        int "large heap malloc threshold"
+        default 512
+        depends on RT_USING_LARGE_HEAP
+        help
+            the memory will allocate in large heap while the allocated size over this
+
+    config RT_LARGE_HEAP_SIZE
+        int "large heap size"
+        default 524288
+        depends on RT_USING_LARGE_HEAP
+        help
+            the remaining memory must be able to accommodate this heap
+
+    endif
+
+config RT_USING_PM_RUNTIME
+    bool "Enable pm runtime"
+    default n
+
+endmenu

bsp/rockchip/common/drivers/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('CommonDrivers', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')

bsp/rockchip/common/drivers/drv_cache.c

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+/**
+  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  ******************************************************************************
+  * @file    drv_cache.c
+  * @version V0.1
+  * @brief   cpu cache interface
+  *
+  * Change Logs:
+  * Date           Author          Notes
+  * 2019-04-01     Cliff.Chen      first implementation
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup RKBSP_Driver_Reference
+ *  @{
+ */
+
+/** @addtogroup Cache
+ *  @{
+ */
+
+/** @defgroup Cache_How_To_Use How To Use
+ *  @{
+
+The Cache driver use to keeping data coherent between cpu and device, it can be used in the following three scenarios:
+
+- **The cpu want to read the latest data that has been modified by device**:
+    - The device modify the data;
+    - The cpu invalidate the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,
+           addr, size);
+    - The cpu read the latest data;
+
+- **The device want to read the latest data that was modified by cpu**:
+    - The cpu modify the data;
+    - The device flush the data by rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, addr, size);
+    - The device read the latest data;
+
+- **The cpu want to execute two code section on the same memory**:
+    - Loading the code A in the memory from start address of ADDR;
+    - Executing the code A;
+    - Loading the code B in the memory from start address of ADDR;
+    - Invalidating by rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, ADDR, size);
+    - Executing the code B
+
+ @} */
+
+#include <rthw.h>
+#include "drv_cache.h"
+#include "hal_base.h"
+
+#if defined(ARCH_ARM_CORTEX_M)
+
+#ifdef RT_USING_CMBACKTRACE
+#include "cm_backtrace.h"
+#endif
+
+/********************* Private MACRO Definition ******************************/
+/** @defgroup CACHE_Private_Macro Private Macro
+ *  @{
+ */
+
+/** @} */  // CACHE_Private_Macro
+
+/********************* Private Structure Definition **************************/
+/** @defgroup CACHE_Private_Structure Private Structure
+ *  @{
+ */
+
+/** @} */  // CACHE_Private_Structure
+
+/********************* Private Variable Definition ***************************/
+/** @defgroup CACHE_Private_Variable Private Variable
+ *  @{
+ */
+
+/** @} */  // CACHE_Private_Variable
+
+/********************* Private Function Definition ***************************/
+/** @defgroup CACHE_Private_Function Private Function
+ *  @{
+ */
+
+/** @} */  // CACHE_Private_Function
+
+/********************* Public Function Definition ****************************/
+
+/** @defgroup CACHE_Public_Functions Public Functions
+ *  @{
+ */
+
+/**
+ * @brief  Enable the icache of cpu.
+ * @attention The cache will be enabled when board initialization, do not dynamically switch cache
+ *      unless specifically required.
+ */
+void rt_hw_cpu_icache_enable(void)
+{
+    HAL_ICACHE_Enable();
+}
+
+/**
+ * @brief  Disable the icache of cpu.
+ * @attention The cache will be enabled when board initialization, do not dynamically switch cache
+ *      unless specifically required.
+ */
+void rt_hw_cpu_icache_disable(void)
+{
+    HAL_ICACHE_Disable();
+}
+
+/**
+ * @brief  Get icache status.
+ * @return 0
+ * @attention Not yet implemnted.
+ */
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+/**
+ * @brief  Icache maintain operation.
+ * @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate.
+ * @param addr: The start address of memory you want maintain.
+ * @param size: The length of memory you want maintain.
+ */
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+    if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        HAL_ICACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+}
+
+/**
+ * @brief  Enable the dcache of cpu.
+ * @attention The cache will be enabled when board initialization, do not dynamically switch cache
+ *      unless specifically required.
+ */
+void rt_hw_cpu_dcache_enable(void)
+{
+    HAL_DCACHE_Enable();
+}
+
+/**
+ * @brief  Disable the dcache of cpu.
+ * @attention The cache will be enabled when board initialization, do not dynamically switch cache
+ *      unless specifically required.
+ */
+void rt_hw_cpu_dcache_disable(void)
+{
+    HAL_DCACHE_Disable();
+}
+
+/**
+ * @brief  Get dcache status.
+ * @return 0
+ * @attention Not yet implemnted.
+ */
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+/**
+ * @brief  Dcache maintain operation.
+ * @param ops: RT_HW_CACHE_INVALIDATE for cache invalidate,
+ *      RT_HW_CACHE_FLUSH for cache clean.
+ * @param addr: The start address of memory you want maintain.
+ * @param size: The length of memory you want maintain.
+ */
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if ((ops & RT_HW_CACHE_FLUSH) && (ops & RT_HW_CACHE_INVALIDATE))
+    {
+        HAL_DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_FLUSH)
+    {
+        HAL_DCACHE_CleanByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        HAL_DCACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+    else
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/**
+ * @brief  Dump ahb error occur in icache & dcache, it called by cache interrupt.
+ * @param fault_handler_lr: The value of LR register.
+ * @param fault_handler_sp: The value of SP register.
+ */
+void cache_dump_ahb_error(uint32_t fault_handler_lr, uint32_t fault_handler_sp)
+{
+    uint32_t addr;
+
+    if (HAL_ICACHE_GetInt())
+    {
+        addr = HAL_ICACHE_GetErrAddr();
+        rt_kprintf("a ahb bus error occur in icache, addr=%p\n", (void *)addr);
+        HAL_ICACHE_ClearInt();
+    }
+
+    if (HAL_DCACHE_GetInt())
+    {
+        addr = HAL_DCACHE_GetErrAddr();
+        rt_kprintf("a ahb bus error occur in dcache, addr=%p\n", (void *)addr);
+        HAL_DCACHE_ClearInt();
+    }
+
+#ifdef RT_USING_CMBACKTRACE
+    cm_backtrace_fault(fault_handler_lr, fault_handler_sp);
+#endif
+}
+
+extern void CACHE_IRQHandler(void);
+
+/**
+ * @brief  Enable cache interrupt and register the handler, it called by board initialization.
+ * @return RT_EOK
+ */
+int rt_hw_cpu_cache_init(void)
+{
+#if defined(ICACHE) || defined(DCACHE)
+    HAL_ICACHE_EnableInt();
+    HAL_DCACHE_EnableInt();
+#if defined(RKMCU_PISCES) || defined(RKMCU_RK2108)
+    rt_hw_interrupt_install(CACHE_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
+    rt_hw_interrupt_umask(CACHE_IRQn);
+#elif defined(RKMCU_RK2206)
+    rt_hw_interrupt_install(CACHE0_I_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
+    rt_hw_interrupt_install(CACHE0_D_IRQn, (rt_isr_handler_t)CACHE_IRQHandler, RT_NULL, RT_NULL);
+    rt_hw_interrupt_umask(CACHE0_I_IRQn);
+    rt_hw_interrupt_umask(CACHE0_D_IRQn);
+#endif
+#endif
+    return RT_EOK;
+}
+
+/** @} */  // CACHE_Public_Functions
+
+#else
+
+RT_WEAK void rt_hw_cpu_icache_enable(void)
+{
+}
+
+RT_WEAK void rt_hw_cpu_icache_disable(void)
+{
+}
+
+RT_WEAK rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+RT_WEAK void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+}
+
+RT_WEAK void rt_hw_cpu_dcache_enable(void)
+{
+}
+
+RT_WEAK void rt_hw_cpu_dcache_disable(void)
+{
+}
+
+RT_WEAK rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+RT_WEAK void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+}
+
+#endif
+
+/** @} */  // Cache
+
+/** @} */  // RKBSP_Driver_Reference