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Merged
theSK2005 merged 19 commits into from
Jul 15, 2026
Merged

feat: [rocjitsu] Flag-Dependent Read/Write Liveness #7384

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6ab8bec
[rocjitsu] Flag-Dependent Read/Write Liveness
theSK2005 Jun 17, 2026
a2fb929
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jun 25, 2026
5e897be
[rocjitsu] regen isa
accauble Jun 26, 2026
d335539
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jun 26, 2026
fc53413
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jun 29, 2026
80ade2a
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 1, 2026
87faec0
pre-commit fix
theSK2005 Jul 1, 2026
40717a1
added vop2 tests
theSK2005 Jul 1, 2026
995c5c7
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 1, 2026
88b74e6
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 7, 2026
98505bc
added check for dpp shift out of bounds where bound_ctrl == 0 which c…
theSK2005 Jul 7, 2026
a47f0ad
added VOP3 DPP coverage
theSK2005 Jul 9, 2026
33a0b6f
pre-commit fix
theSK2005 Jul 9, 2026
915a58f
derive VOP2/VOP2 destination ref from to_register_ref so width = 1 is…
theSK2005 Jul 10, 2026
7016060
added VOP3P and VOP33_SDST_ENC handling
theSK2005 Jul 10, 2026
9503713
updated implicit uses for DPP/SDWA to only add VGPRs to match the emu…
theSK2005 Jul 10, 2026
9b947e4
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 10, 2026
6849be2
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 14, 2026
32524c2
Merge branch 'develop' into users/skushwah/liveness-analysis-rw-flags
theSK2005 Jul 14, 2026
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17 changes: 17 additions & 0 deletions emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1653,6 +1653,23 @@ def _encoding_implicit_uses_impl(
'static_cast<uint16_t>(inst_.saddr), 2});'
'}'
)
# SDWA dst_unused:PRESERVE keeps the untouched bytes of the old
# destination, so the instruction reads vdst. DPP with partial
# row or bank mask keeps untouched lanes. Surfacing here so
# liveness and def/use dataflow see the dependency.
if (
inst_enc.enc_name.upper() in ('ENC_VOP1', 'ENC_VOP2')
Comment thread
theSK2005 marked this conversation as resolved.
Resolved
and 'vdst' in enc_field_names
):
return (
'bool sdwa_preserve = sdwa_dst_sel_ != amdgpu::sdwa::DWORD && '
'sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;'
'bool dpp_partial = inst_.src0 == amdgpu::SRC_DPP && '
'(dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF); '
'if (sdwa_preserve || dpp_partial) '
'uses.expand(RegisterRef{RegClass::VGPR, '
'static_cast<uint16_t>(inst_.vdst), 1});'
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Comment thread
theSK2005 marked this conversation as resolved.
Resolved
)
return ''

def _enc_field_at_bit(self, enc_name: str, bit_offset: int) -> str | None:
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down Expand Up @@ -168,6 +177,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down Expand Up @@ -131,6 +132,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down Expand Up @@ -168,6 +177,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna2/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down Expand Up @@ -131,6 +132,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down Expand Up @@ -168,6 +177,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna3/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down Expand Up @@ -131,6 +132,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down Expand Up @@ -162,6 +171,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249;
}
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down Expand Up @@ -129,6 +130,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_dpp();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -171,6 +171,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return (inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 254);
Expand Down Expand Up @@ -223,6 +232,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return (inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 254);
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/gfx1250/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_lit64();
Expand Down Expand Up @@ -145,6 +146,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool has_lit64();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 249;
Expand Down Expand Up @@ -162,6 +171,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 249;
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/encodings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
using OpEncoding = Vop1MachineInst;
Expand Down Expand Up @@ -129,6 +130,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool hasImpliedLiteral();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 249;
Expand Down Expand Up @@ -162,6 +171,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 &&
inst_.src0 != 249;
Expand Down
2 changes: 2 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/encodings.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ class Smem : public IsaInstruction<Isa> {
class Vop1 : public IsaInstruction<Isa> {
public:
Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
using OpEncoding = Vop1MachineInst;
Expand Down Expand Up @@ -129,6 +130,7 @@ class Vopc : public IsaInstruction<Isa> {
class Vop2 : public IsaInstruction<Isa> {
public:
Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn);
void implicit_uses(RegisterSet &uses) const override;
bool default_encoding();
bool has_lit();
bool hasImpliedLiteral();
Expand Down
18 changes: 18 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/encodings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,15 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe
size_ += sizeof(MachineInst);
}

void Vop1::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop1::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255;
}
Expand Down Expand Up @@ -160,6 +169,15 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe
literal_ = reinterpret_cast<const uint32_t *>(inst)[1];
}

void Vop2::implicit_uses(RegisterSet &uses) const {
bool sdwa_preserve =
sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE;
bool dpp_partial =
inst_.src0 == amdgpu::SRC_DPP && (dpp_row_mask_ != 0xF || dpp_bank_mask_ != 0xF);
if (sdwa_preserve || dpp_partial)
uses.expand(RegisterRef{RegClass::VGPR, static_cast<uint16_t>(inst_.vdst), 1});
}

bool Vop2::default_encoding() {
return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255;
}
Expand Down
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