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Merged
kuhar merged 1 commit into from
Nov 3, 2026
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[rocjitsu] Compact generated operand storage #14779

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7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16746,7 +16746,7 @@ def gen_operand(self) -> None:
cgen.Line(
f'{operand_base_decl}'
'public:\n'
' enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };\n'
' enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };\n'
' static constexpr bool kStaticRegisterAccess = true;\n'
f'{operand_ctor_decl}'
' Operand(int size_bits, OperandType opr_type, int encoding_value,\n'
Expand All @@ -16761,11 +16761,12 @@ def gen_operand(self) -> None:
f'{execution_backend_public_decl}'
f'{execution_decls}'
' uint64_t widened_literal32_value() const;\n'
' // Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.\n'
' uint64_t literal64_value_ = 0;\n'
' std::optional<Literal32Widening> literal32_widening_;\n'

@IanWood1 IanWood1 Nov 3, 2026

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Moving this field before execution_backend_ lets it use part of the four bytes of tail padding in the base class (IsaOperand<Isa>), leaving room at the end for future flags without increasing the operand size.

' uint16_t literal16_display_value_ = 0;\n'
' bool has_literal16_display_ = false;\n'
' uint64_t literal64_value_ = 0;\n'
' bool has_literal64_ = false;\n'
' std::optional<Literal32Widening> literal32_widening_;\n'
f'{packed_16bit_field}'
'};'
)
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7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace cdna1 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace cdna1
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace cdna2 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace cdna2
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace cdna3 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace cdna3
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace cdna4 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace cdna4
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace cdna5 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value, bool packed_16bit_source = false,
bool packed_16bit_dst = false);
Expand Down Expand Up @@ -133,11 +133,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
bool packed_16bit_source_ = false;
bool packed_16bit_dst_ = false;
std::optional<uint32_t> resolved_vgpr_offset_exec(const amdgpu::Wavefront &wf) const;
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace rdna1 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace rdna1
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace rdna2 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value);
Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value,
Expand Down Expand Up @@ -130,11 +130,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
};

} // namespace rdna2
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ namespace rdna3 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value, bool packed_16bit_source = false,
bool packed_16bit_dst = false);
Expand Down Expand Up @@ -133,11 +133,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
bool packed_16bit_source_ = false;
bool packed_16bit_dst_ = false;
std::optional<uint32_t> resolved_vgpr_offset_exec(const amdgpu::Wavefront &wf) const;
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.h
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Expand Up @@ -18,7 +18,7 @@ namespace rdna3_5 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value, bool packed_16bit_source = false,
bool packed_16bit_dst = false);
Expand Down Expand Up @@ -133,11 +133,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
bool packed_16bit_source_ = false;
bool packed_16bit_dst_ = false;
std::optional<uint32_t> resolved_vgpr_offset_exec(const amdgpu::Wavefront &wf) const;
Expand Down
7 changes: 4 additions & 3 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ namespace rdna4 {

class Operand final : public IsaOperand<Isa> {
public:
enum class Literal32Widening { ZeroExtend, SignExtend, Replicate32, F64HighBits };
enum class Literal32Widening : uint8_t { ZeroExtend, SignExtend, Replicate32, F64HighBits };
static constexpr bool kStaticRegisterAccess = true;
Operand(int size_bits, OperandType opr_type, int encoding_value, bool packed_16bit_source = false,
bool packed_16bit_dst = false);
Expand Down Expand Up @@ -133,11 +133,12 @@ class Operand final : public IsaOperand<Isa> {
void simd_notify_write_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
void simd_notify_write64_mut_exec(amdgpu::Wavefront &, uint64_t, uint8_t) const;
uint64_t widened_literal32_value() const;
// Pack literal state with the byte-sized widening enum to keep operands at 64 bytes.
uint64_t literal64_value_ = 0;
std::optional<Literal32Widening> literal32_widening_;
uint16_t literal16_display_value_ = 0;
bool has_literal16_display_ = false;
uint64_t literal64_value_ = 0;
bool has_literal64_ = false;
std::optional<Literal32Widening> literal32_widening_;
bool packed_16bit_source_ = false;
bool packed_16bit_dst_ = false;
std::optional<uint32_t> resolved_vgpr_offset_exec(const amdgpu::Wavefront &wf) const;
Expand Down
10 changes: 7 additions & 3 deletions emulation/rocjitsu/tests/decode_smoke_test.cpp
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Expand Up @@ -109,10 +109,14 @@ constexpr uint32_t make_cdna1_sop1(uint32_t sdst, uint32_t ssrc0) {
return 0xBE800000u | ((sdst & 0x7Fu) << 16) | (ssrc0 & 0xFFu);
}

TEST(OperandLayoutTest, DeferredSelectorStateFitsExistingPadding) {
TEST(OperandLayoutTest, GeneratedOperandsUse64Bytes) {
EXPECT_EQ(sizeof(Instruction), 192u);
EXPECT_EQ(sizeof(Operand), 32u);
EXPECT_EQ(sizeof(cdna5::Operand), 80u);
EXPECT_EQ(sizeof(cdna5::VAddF32Vop3), 480u);
// Cover generator profiles with and without packed 16-bit state.
EXPECT_EQ(sizeof(cdna4::Operand), 64u);
EXPECT_EQ(sizeof(cdna5::Operand), 64u);
EXPECT_EQ(sizeof(cdna5::VAddF32Vop3), 432u);
EXPECT_EQ(sizeof(cdna5::Vopd), 864u);
}

TEST(OperandLayoutTest, DecodedVectorRegistersExcludeScalarAndLiteralSelectors) {
Expand Down
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