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fix(rocr): Select I$ and GL2 invalidation for gfx125x code caches #13924

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Merged
renjithravindrankannath merged 1 commit into from
Nov 3, 2026
Merged

fix(rocr): Select I$ and GL2 invalidation for gfx125x code caches #13924

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11 changes: 11 additions & 0 deletions projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_gpu_pm4.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,11 +85,22 @@
#define PM4_ACQUIRE_MEM_DW4_COHER_BASE_HI(x) ((x >> 40) & 0xFFFFFFU)
#define PM4_ACQUIRE_MEM_DW7_GCR_CNTL(x) (((x) & 0x7FFFFU) << 0)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) (((x) & 0x3U) << 0)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV_ALL 1U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV_RANGE 2U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GLK_INV (1U << 7)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GLV_INV (1U << 8)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL1_INV (1U << 9)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) (((x) & 0x3U) << 11)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_ALL 0U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_VOL 1U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_RANGE 2U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_FIRST_LAST 3U
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_INV (1U << 14)
# define PM4_ACQUIRE_MEM_GCR_CNTL_GL2_WB (1U << 15)
# define PM4_ACQUIRE_MEM_GCR_CNTL_SEQ(x) (((x) & 0x3U) << 16)
# define PM4_ACQUIRE_MEM_GCR_CNTL_SEQ_PARALLEL 0U
# define PM4_ACQUIRE_MEM_GCR_CNTL_SEQ_FORWARD 1U
# define PM4_ACQUIRE_MEM_GCR_CNTL_SEQ_REVERSE 2U
#define PM4_RELEASE_MEM_DW1_EVENT_INDEX(x) (((x) & 0xFU) << 8)
# define PM4_RELEASE_MEM_EVENT_INDEX_AQL 0x7U

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19 changes: 18 additions & 1 deletion projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3560,9 +3560,26 @@ void GpuAgent::InvalidateCodeCaches(void *ptr, size_t size) {
PM4_ACQUIRE_MEM_COHER_CNTL_TC_WB_ACTION_ENA);

cache_inv_size_dw = 7;
} else if (supported_isas()[0]->GetMajorVersion() == 12 &&
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supported_isas()[0]->GetMinorVersion() == 5) {
// K$/V$ are maintained by dispatch; GCR_CNTL[9] is reserved.
// Select only I$/GL2 maintenance, using the common base/size encoding.
cache_inv[7] = PM4_ACQUIRE_MEM_DW7_GCR_CNTL(
PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV(
ptr ? PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV_RANGE
: PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV_ALL) |
PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(
ptr ? PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_RANGE
: PM4_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE_ALL) |
PM4_ACQUIRE_MEM_GCR_CNTL_GL2_INV |
PM4_ACQUIRE_MEM_GCR_CNTL_SEQ(
PM4_ACQUIRE_MEM_GCR_CNTL_SEQ_REVERSE));

cache_inv_size_dw = 8;
} else {
cache_inv[7] = PM4_ACQUIRE_MEM_DW7_GCR_CNTL(
PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1) |
PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV(
PM4_ACQUIRE_MEM_GCR_CNTL_GLI_INV_ALL) |
PM4_ACQUIRE_MEM_GCR_CNTL_GLK_INV |
PM4_ACQUIRE_MEM_GCR_CNTL_GLV_INV |
PM4_ACQUIRE_MEM_GCR_CNTL_GL1_INV |
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