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fix(rocr): Select I$ and GL2 invalidation for gfx125x code caches - #13924
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K$ and V$ are maintained by dispatch, and GCR_CNTL[9] is reserved on gfx125x. Use RANGE for a non-null pointer and ALL for a null pointer, sequenced in reverse. Keep the common base/size encoding and leave other ISA paths unchanged. Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: David Yat Sin <David.YatSin@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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CI test failures are unrelated to this changeThis PR only changes Completed test failures:
The two Multi-Arch CI Summary failures come from earlier runs that were cancelled (
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Re-running the failed CI tests on TheRock Multi-Arch CI run 39637381994:
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Re-running the failed CI tests on https://github.com/ROCm/rocm-systems/actions/runs/39637381994 (attempt 3):
The Test step timed out after 20 minutes. This PR only changes code-cache invalidation for gfx125x, so gfx94X stays on the existing acquire-mem packet. Multi-Arch CI Summary will run again after that job finishes. |
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Bypassing the rule due to known CI job failure. |
caches (#13924) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Summary On gfx125x, code-cache invalidation selects only the instruction cache and GL2. Scalar and vector caches are maintained by dispatch, and GCR_CNTL[9] is reserved. A non-null pointer uses RANGE, a null pointer uses ALL, and the two operations are sequenced in reverse. The shared base/size encoding is unchanged, and every other ISA keeps its existing acquire-mem packet. ## JIRA ID The internal change did not name a ticket. ## Test plan - [x] On gfx125x, load a code object and launch a kernel so the non-null RANGE invalidation runs. c07-1 (gfx1250, official amdgpu 7.1.0-2424461), kernel result 1. Two RANGE packets: isa=12.5, 8 dwords, header `c0065800`, DW7 `00025002`. Size granules matched (14449 → `0x39`, 36864 → `0x90`) and the base fields matched the pointers. - [x] On gfx125x, exercise the null-pointer ALL invalidation and confirm it completes. Same run submitted one null packet and waited for it: header `c0065800`, DW2/DW3 `ffffffff`/`ff`, DW7 `00024001`. Product callers pass the code-object pointer, so this packet was submitted once from the test build. - [x] gfx1100 on dayatsin-test-01 (gfx10+, not gfx125x) submits the existing acquire-mem packet. - [x] gfx950 on e3-2b (pre-gfx10) submits the existing acquire-mem packet. Made with [Cursor](https://cursor.com) Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: David Yat Sin <David.YatSin@amd.com> Co-authored-by: Shane Xiao <shane.xiao@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com> [rocm-systems] ROCm/rocm-systems#13924 (commit a9c3b00)
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Summary
On gfx125x, code-cache invalidation selects only the instruction cache and GL2. Scalar and vector caches are maintained by dispatch, and GCR_CNTL[9] is reserved. A non-null pointer uses RANGE, a null pointer uses ALL, and the two operations are sequenced in reverse. The shared base/size encoding is unchanged, and every other ISA keeps its existing acquire-mem packet.
JIRA ID
The internal change did not name a ticket.
Test plan
c0065800, DW700025002. Size granules matched (14449 →0x39, 36864 →0x90) and the base fields matched the pointers.c0065800, DW2/DW3ffffffff/ff, DW700024001. Product callers pass the code-object pointer, so this packet was submitted once from the test build.Made with Cursor