Skip to content

Revert "[rocjitsu] Clear the reserved wave32 descriptor bit on gfx125x" #13366

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
kuhar merged 1 commit into from
Oct 13, 2026
Merged

Revert "[rocjitsu] Clear the reserved wave32 descriptor bit on gfx125x" #13366

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 3 additions & 5 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -166,12 +166,10 @@ void insert_file_bytes(std::vector<uint8_t> &image, Elf64_Ehdr &ehdr,
return text_index;
}

[[nodiscard]] bool target_has_wavefront_size_bit(rj_code_arch_t arch) {
// ENABLE_WAVEFRONT_SIZE32 selects between two supported wave sizes. Wave32-only
// gfx125x reserves the bit and requires it to be zero.
[[nodiscard]] bool target_supports_wave32(rj_code_arch_t arch) {
return arch == ROCJITSU_CODE_ARCH_RDNA1 || arch == ROCJITSU_CODE_ARCH_RDNA2 ||
arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 ||
arch == ROCJITSU_CODE_ARCH_RDNA4;
arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5;
}

[[nodiscard]] bool target_uses_gfx10_plus_mode_bits(rj_code_arch_t arch) {
Expand Down Expand Up @@ -267,7 +265,7 @@ void insert_file_bytes(std::vector<uint8_t> &image, Elf64_Ehdr &ehdr,
AMDHSA_BITS_SET(desc.compute_pgm_rsrc1, kd::COMPUTE_PGM_RSRC1_FWD_PROGRESS, 1);
}

if (target_has_wavefront_size_bit(target_arch)) {
if (target_supports_wave32(target_arch)) {
const uint32_t wave32 = translation.target_wave_size == 32 ? 1u : 0u;
AMDHSA_BITS_SET(desc.kernel_code_properties, kd::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
wave32);
Expand Down
48 changes: 0 additions & 48 deletions emulation/rocjitsu/tests/dbt/translate_test.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2879,54 +2879,6 @@ TEST(CodeObjectPatcher, AppliesArchSpecificWgpModeBit) {
EXPECT_EQ(AMDHSA_BITS_GET(*gfx1250_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS), 1u);
}

TEST(CodeObjectPatcher, WavefrontSizeBitIsReservedUnlessTargetSupportsBothSizes) {
using namespace rocr::llvm::amdhsa;

struct Target {
rj_code_arch_t arch;
uint8_t wave_size;
uint32_t expected_bit;
};
const Target targets[] = {
{ROCJITSU_CODE_ARCH_CDNA4, 64, 0}, {ROCJITSU_CODE_ARCH_CDNA5, 32, 0},
{ROCJITSU_CODE_ARCH_RDNA1, 32, 1}, {ROCJITSU_CODE_ARCH_RDNA1, 64, 0},
{ROCJITSU_CODE_ARCH_RDNA2, 32, 1}, {ROCJITSU_CODE_ARCH_RDNA2, 64, 0},
{ROCJITSU_CODE_ARCH_RDNA3, 32, 1}, {ROCJITSU_CODE_ARCH_RDNA3, 64, 0},
{ROCJITSU_CODE_ARCH_RDNA3_5, 32, 1}, {ROCJITSU_CODE_ARCH_RDNA3_5, 64, 0},
{ROCJITSU_CODE_ARCH_RDNA4, 32, 1}, {ROCJITSU_CODE_ARCH_RDNA4, 64, 0},
};
for (const auto &target : targets) {
for (const uint32_t source_bit : {0u, 1u}) {
SCOPED_TRACE(::testing::Message()
<< "arch=" << target.arch << " wave_size=" << unsigned(target.wave_size)
<< " source_bit=" << source_bit);
auto image = make_minimal_amdgpu_elf_with_descriptor_after_text();
AmdGpuCodeObject probe(image.data(), image.size());
ASSERT_TRUE(probe.is_valid());
const Section *rodata = find_section(probe, ".rodata");
ASSERT_NE(rodata, nullptr);
const uint64_t descriptor_offset = rodata->sectionOffset();
auto descriptor = read_kernel_descriptor_for_test(rodata->data());
AMDHSA_BITS_SET(descriptor.kernel_code_properties,
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, source_bit);
write_kernel_descriptor_for_test(image.data() + descriptor_offset, descriptor);

AmdGpuCodeObject source(image.data(), image.size());
KdTranslation translation{};
translation.descriptor_file_offset = descriptor_offset;
translation.target_wave_size = target.wave_size;
CodeObjectPatcher patcher(source);
ASSERT_TRUE(patcher.apply_kernel_descriptor_translation(translation, target.arch));
const auto patched_image = patcher.emit();
const auto patched =
read_kernel_descriptor_for_test(patched_image.data() + descriptor_offset);
EXPECT_EQ(AMDHSA_BITS_GET(patched.kernel_code_properties,
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32),
target.expected_bit);
}
}
}

TEST(CodeObjectPatcher, PreservesPrivateEnableForZeroFixedDynamicStack) {
using namespace rocr::llvm::amdhsa;

Expand Down
Loading