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[rocjitsu] Clear the reserved wave32 descriptor bit on gfx125x - #13141
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Gfx125x only supports wave32, so ENABLE_WAVEFRONT_SIZE32 is reserved and must be zero. LLVM now emits zero and rejects descriptors with the bit set when disassembling them. RocJITsu's resource patcher incorrectly sets it based on the target wave size during B0-to-A0 translation. Restrict the bit to RDNA targets, which support both wave sizes, and rename the predicate to describe descriptor-bit availability. This also clears the bit when translating objects produced by older compilers. Cover clear and set source bits, CDNA fixed wave sizes, and RDNA wave32/wave64 selection. The regression fails before the fix. With the fix, the reproduced descriptor matches LLVM's output and disassembles successfully; only the reserved bit changes in the translated ELF. Validation: 242 focused CPU tests and repository pre-commit checks pass. LLVM change: llvm/llvm-project#229162
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accauble
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chinmaydd
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Thank you for the prompt fix. LGTM
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gfx1250 B0-to-A0 translation baselineWarning This PR changes 20128 translated output SHA-256 value(s). Compared
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anujshuk-amd
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Gfx125x only supports wave32, so ENABLE_WAVEFRONT_SIZE32 is reserved and must be zero. LLVM now emits zero and rejects descriptors with the bit set when disassembling them. RocJITsu's resource patcher incorrectly sets it based on the target wave size during B0-to-A0 translation. Restrict the bit to RDNA targets, which support both wave sizes, and rename the predicate to describe descriptor-bit availability. This also clears the bit when translating objects produced by older compilers. Cover clear and set source bits, CDNA fixed wave sizes, and RDNA wave32/wave64 selection. The regression fails before the fix. With the fix, the reproduced descriptor matches LLVM's output and disassembles successfully; only the reserved bit changes in the translated ELF. Validation: 242 focused CPU tests and repository pre-commit checks pass. LLVM change: llvm/llvm-project#229162 JIRA ID: ROCM-32508
ScottTodd
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…x" [bkc 20261013] (#13481) Cherry-picks: - #13366 Cherry-pick of the revert of #13141 (merged to `develop` as 73d0efc) into `release/bkc/therock-10.2-20261013` for BKC MI455 26.13. #13141 broke gfx1250 A0 environments (B0→A0 translation clears `ENABLE_WAVEFRONT_SIZE32` in the kernel descriptor). This blocks BKC MI455 26.13. Snap build #301 does not include the fix. Jira: [ROCM-32640](https://amd-hub.atlassian.net/browse/ROCM-32640) The cherry-pick applies cleanly. Both affected files on the release branch are identical to the revert's parent commit, so the diff is the same as #13366. 🤖 Generated with [Claude Code](https://claude.com/claude-code) [ROCM-32640]: https://amd-hub.atlassian.net/browse/ROCM-32640?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ Co-authored-by: Jakub Kuderski <jakub@nod-labs.com>
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Gfx125x only supports wave32, so ENABLE_WAVEFRONT_SIZE32 is reserved and must be zero. LLVM now emits zero and rejects descriptors with the bit set when disassembling them. RocJITsu's resource patcher incorrectly sets it based on the target wave size during B0-to-A0 translation.
Restrict the bit to RDNA targets, which support both wave sizes, and rename the predicate to describe descriptor-bit availability. This also clears the bit when translating objects produced by older compilers.
Cover clear and set source bits, CDNA fixed wave sizes, and RDNA wave32/wave64 selection. The regression fails before the fix. With the fix, the reproduced descriptor matches LLVM's output and disassembles successfully; only the reserved bit changes in the translated ELF.
Validation: 242 focused CPU tests and repository pre-commit checks pass.
LLVM change: llvm/llvm-project#229162
JIRA ID:
ROCM-32508