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fix(tensilelite): generate aux output E in persistent kernels - #12869

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jaopaulolc merged 9 commits into
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users/jolabega/fix-tensilelite-streamk-aux-codegen
Oct 7, 2026
Merged

jaopaulolc merged 9 commits into
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users/jolabega/fix-tensilelite-streamk-aux-codegen

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@jaopaulolc jaopaulolc commented Oct 1, 2026 •

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JIRA ID : AIHPBLAS-4984

Motivation

TensileLite generates the GEMM kernels that hipBLASLt runs. Some also write an auxiliary output, E, holding the values before the activation. Persistent kernels (TileProcessingStrategy StreamK or DataParallel) loop over output tiles. With E enabled, generating any persistent kernel failed with a TypeError.

Technical Details

  • Persistent kernels set GlobalSplitU to 0. The epilogue already stored E for them, but the E address and row offset setup in AsmStoreState.py, AsmAddressCalculation.py, ComputeStoreVgprs.py and LSU.py required GlobalSplitU 1. It now also accepts isPersistent, as bias does.
  • StreamK.py: the tree-reduction fixup reserved 2 SGPRs but used 3. With E, the third held part of the E buffer address, and the kernel faulted. It now reserves 3.
  • Solution.py rejects E with StoreRemapVectorWidth for persistent kernels, as for GlobalSplitU 1.
  • New tests in Tensile/Tests/common/streamk/gfx950/, FP16 with bias and E plus a gradient case: sk_hgemm_use_e.yaml covers each WorkAssignment, with and without tree reduction, and data_parallel_static_hgemm_use_e.yaml covers DataParallel.

Test Plan

From projects/hipblaslt/tensilelite, run tox -e py3 -- -m common -k hgemm_use_e.

Test Result

On an MI355X (gfx950), both tests fail on develop with the TypeError and pass with this change (176 of 176 cases, D and E validated). The 50 existing persistent, aux output and gradient common tests pass. Unit tests show no new failures. Automated GitHub checks are pending.

Submission Checklist

Risk level

Low (2/5): only persistent kernels with E change, and those failed to generate before. Tree-reduction kernels without E generate identical code.

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✅ All Checks Passed — Ready for Review

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📝 PR Description ✅ Pass —
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🧪 Unit Test ⚠️ Warning Error: Source/code files changed without an accompanying unit test.
Expected: add at least one test file named like test_<name>.py / test_<name>.cpp (or <name>_test.*).
Current: code file(s) changed: projects/hipblaslt/tensilelite/Tensile/AsmAddressCalculation.py, projects/hipblaslt/tensilelite/Tensile/AsmStoreState.py, projects/hipblaslt/tensilelite/Tensile/Components/ComputeStoreVgprs.py, projects/hipblaslt/tensilelite/Tensile/Components/LSU.py, projects/hipblaslt/tensilelite/Tensile/Components/StreamK.py (+1 more); no test file found
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🎉 All checks passed! This PR is ready for review.

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Codecov Report

❌ Patch coverage is 66.66667% with 5 lines in your changes missing coverage. Please review.

Files with missing lines Patch % Lines
...cts/hipblaslt/tensilelite/Tensile/AsmStoreState.py 66.67% 2 Missing ⚠️
...lt/tensilelite/Tensile/SolutionStructs/Solution.py 0.00% 1 Missing and 1 partial ⚠️
...ts/hipblaslt/tensilelite/Tensile/Components/LSU.py 50.00% 0 Missing and 1 partial ⚠️

❌ Your project check has failed because the head coverage (49.31%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage.

Additional details and impacted files
@@             Coverage Diff             @@
##           develop   #12869      +/-   ##
===========================================
- Coverage    71.93%   70.95%   -0.97%     
===========================================
  Files         2863     2946      +83     
  Lines       472701   485433   +12732     
  Branches     69827    70078     +251     
===========================================
+ Hits        340000   344425    +4425     
- Misses      109118   117059    +7941     
- Partials     23583    23949     +366     
Flag Coverage Δ *Carryforward flag
TensileLite-CPP 49.31% <ø> (-0.02%) ⬇️
TensileLite-Unit 83.28% <66.67%> (+<0.01%) ⬆️
hipBLAS 90.62% <ø> (ø) Carriedforward from df06c92
hipBLASLt 38.92% <ø> (ø)
hipCUB 82.68% <ø> (ø) Carriedforward from df06c92
hipDNN 86.64% <ø> (+<0.01%) ⬆️ Carriedforward from df06c92
hipFFT 54.32% <ø> (+10.89%) ⬆️ Carriedforward from df06c92
hipRAND 76.12% <ø> (ø) Carriedforward from df06c92
hipSOLVER 68.96% <ø> (ø) Carriedforward from df06c92
hipSPARSE 86.99% <ø> (ø) Carriedforward from df06c92
rocBLAS 48.25% <ø> (-<0.01%) ⬇️ Carriedforward from df06c92
rocFFT 47.42% <ø> (-0.20%) ⬇️ Carriedforward from df06c92
rocRAND 57.42% <ø> (-0.03%) ⬇️ Carriedforward from df06c92
rocSOLVER 76.83% <ø> (+<0.01%) ⬆️ Carriedforward from df06c92
rocSPARSE 74.75% <ø> (+0.12%) ⬆️ Carriedforward from df06c92
rocThrust 78.45% <ø> (-14.70%) ⬇️ Carriedforward from df06c92

*This pull request uses carry forward flags. Click here to find out more.

Files with missing lines Coverage Δ
...laslt/tensilelite/Tensile/AsmAddressCalculation.py 64.55% <100.00%> (ø)
...ensilelite/Tensile/Components/ComputeStoreVgprs.py 93.30% <100.00%> (+0.03%) ⬆️
...ipblaslt/tensilelite/Tensile/Components/StreamK.py 82.48% <100.00%> (ø)
...ts/hipblaslt/tensilelite/Tensile/Components/LSU.py 77.00% <50.00%> (+0.06%) ⬆️
...cts/hipblaslt/tensilelite/Tensile/AsmStoreState.py 72.06% <66.67%> (ø)
...lt/tensilelite/Tensile/SolutionStructs/Solution.py 64.33% <0.00%> (ø)

... and 172 files with indirect coverage changes

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A persistent TileProcessingStrategy (StreamK or DataParallel) sets
GlobalSplitU to 0. The epilogue already emitted E stores for persistent
kernels, but the E address registers, row offset and row advance only
checked GlobalSplitU == 1, so generating any persistent kernel with E
failed with a TypeError.

Set up the E address and row offset for the persistent final store with
isPersistent, the same way bias and ScaleAlphaVec already do. In the
StreamK tree-reduction fixup, check out the 3 SGPRs the flag wait uses
instead of 2; with E, the third one was the low word of the E buffer
address and the kernel faulted. Reject E with StoreRemapVectorWidth for
persistent kernels, as for GlobalSplitU == 1.

Add gfx950 common tests that validate D and E for StreamK with each
WorkAssignment, with and without tree reduction, and for DataParallel,
each with a gradient case that reads E.
@jaopaulolc
jaopaulolc force-pushed the users/jolabega/fix-tensilelite-streamk-aux-codegen branch from 35fa576 to 74e2139 Compare October 2, 2026 17:14
@jaopaulolc jaopaulolc changed the title fix(tensilelite): generate aux output E in Stream-K kernels fix(tensilelite): generate aux output E in persistent kernels Oct 2, 2026
@jaopaulolc
jaopaulolc marked this pull request as ready for review October 2, 2026 18:19
@jaopaulolc
jaopaulolc requested a review from a team as a code owner October 2, 2026 18:19
@jaopaulolc jaopaulolc added the rocm:gemm algos Label to identify PRs of the GEMM Algorithms team. label Oct 2, 2026

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Does this also work with Stream-K + ParallelReduction (post kerenl code path)?

The sk_hgemm_use_e sizes all select tree reduction. Add 512x512x8192:
with 16 tiles and 128 iterations per tile, origami selects parallel
reduction for StaticGrid and Hybrid, so the GEMM kernel writes split
partials to the workspace and the post kernel applies bias and the
activation and writes E.
@jaopaulolc

jaopaulolc commented Oct 5, 2026 •

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Does this also work with Stream-K + ParallelReduction (post kerenl code path)?
@AlexBrownAMD Yes. https://github.com/ROCm/rocm-libraries/pull/12869/changes#diff-60c71e6f5dfc31abb1a27442227b9bf495d04c7e4f001a3169c74228f99fd447R56-R57

jaopaulolc added a commit that referenced this pull request Oct 5, 2026
TensileLite now generates Stream-K kernels that write the auxiliary
output E (#12869's fix), so the Origami predictor no longer drops the
catalog's Hybrid Stream-K candidates when the request has one. The
knowledge test expects an auxiliary output to keep every candidate, and
the docs drop the limitation.
@jaopaulolc
jaopaulolc enabled auto-merge (squash) October 5, 2026 21:28
@jaopaulolc
jaopaulolc merged commit 369d5b7 into develop Oct 7, 2026
232 of 246 checks passed
@jaopaulolc
jaopaulolc deleted the users/jolabega/fix-tensilelite-streamk-aux-codegen branch October 7, 2026 21:30
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