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add tuned logic files for resnet and inception sizes #644

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Merged
wbgilmartin merged 1 commit into from
Aug 13, 2019
Merged

add tuned logic files for resnet and inception sizes #644

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16,562 changes: 16,546 additions & 16 deletions library/src/blas3/Tensile/Logic/archive/vega20_Cijk_Ailk_Bjlk_SB.yaml
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12,964 changes: 12,944 additions & 20 deletions library/src/blas3/Tensile/Logic/archive/vega20_Cijk_Ailk_Bljk_SB.yaml
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18,556 changes: 18,504 additions & 52 deletions library/src/blas3/Tensile/Logic/archive/vega20_Cijk_Alik_Bljk_SB.yaml
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59,908 changes: 46,484 additions & 13,424 deletions library/src/blas3/Tensile/Logic/asm_ci/vega20_Cijk_Ailk_Bjlk_SB.yaml
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76,970 changes: 51,409 additions & 25,561 deletions library/src/blas3/Tensile/Logic/asm_ci/vega20_Cijk_Ailk_Bljk_SB.yaml
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71,762 changes: 54,333 additions & 17,429 deletions library/src/blas3/Tensile/Logic/asm_ci/vega20_Cijk_Alik_Bljk_SB.yaml
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59,908 changes: 46,484 additions & 13,424 deletions library/src/blas3/Tensile/Logic/asm_full/vega20_Cijk_Ailk_Bjlk_SB.yaml
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