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[PERF] Add opt-in atomic stage2 override - #4556
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Signed-off-by: Vorapol Assavasangthong <Vorapol.Assavasangthong@amd.com> Co-authored-by: Santosh Hiremath <Santosh.Hiremath@amd.com>
Verify tuned lookup rewrites stage2 metadata and that MoE sorting receives atomic accumulation, including fallback and force-reduce precedence. Signed-off-by: Vorapol Assavasangthong <Vorapol.Assavasangthong@amd.com>
Use Ruff's preferred import form so the PR passes the current style gate. Signed-off-by: Vorapol Assavasangthong <Vorapol.Assavasangthong@amd.com>
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The rebased branch is mergeable and the PR-specific tests pass, but one standard-test shard needs a maintainer rerun:
Could a maintainer please rerun the failed shard? |
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close this now as alternative fixing at config level #5155 has now merged |
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Summary
Add an opt-in
AITER_FLYDSL_FORCE_ATOMIC=1override that replaces an eligible tuned FlyDSL stage-2_reducekernel with its registered_atomicsibling while constructing MoE metadata.Safety and precedence are explicit:
AITER_FLYDSL_FORCE_REDUCE=1takes precedence when both variables are set;Motivation and measured result
Using #4554's Qwen3-VL tuning rows on 8× MI355X, 1024 input/output tokens, concurrency 4:
_reduce: 375.19 output tok/s, 889.47 total tok/s;_atomic: 391.46 output tok/s, 928.27 total tok/s;The opt-in override recovers approximately 4.3% output throughput for this point while retaining safe fallback behavior.
Qwen3-VL integration stack
b0cc5392; provides full strided MRoPE KV-cache support.Rebase provenance
main:fc2e5d57fb5b8ad8e7e23f7103071dde798ea6185390e8912bcfd58f6132a30428dcb5a2bf7744deValidation
pytest -q op_tests/test_fused_moe_kernel_selection.py— 7 passed.FORCE_REDUCEprecedence, and the full tuned-config lookup → metadata rewrite → MoE-sorting accumulation path.git diff --check— passed.test_moe_2stage.pyshard that exhausted GPU memory with the opt-in override unset; a maintainer rerun has been requested.