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Merging into master for 0.8 release #99

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merged 85 commits into from
Jun 24, 2020
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@mn416 mn416 commented Jun 24, 2020

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A 2D mesh of board routers (one per board) now connects together the
2D NoCs on each board.  This means that message can pass over a board
without travesing the NoC.  The per-board router is not yet
programmable, but that is direction we are heading.
Support routing-key-based send operations, but programmable routers
don't yet interpret routing keys.
Need to support inflight request info for programmable routers now, in
addition to caches.  Therefore, generalise the info field in a
DRAMResp.  Need to check that the optimiser does what I expect in this
case, i.e. throws away unused bits in the info field.
(But doesn't compile yet)
(Compiles but untested)
(Works, but only tests one type of routing record so far)
These work.  Still need to test RR records, and multi-beat records.
Working fine but needed to clarify the docs: the size field in a beat
is the number of records, not the number of chunks.
This is to distinguish (existing) thread-level routing tables from
board-level routing tables (to come).
(Builds but untested)
The 'active' condition in the fetcher was inverted, and also referred
to the wrong state variable.
Missing 'return' statement, and missing use of 'offset' when uploading
routing tables.  The POLite heat grid now appears to work in
simulation.  Ready to try things on FPGA.
mn416 and others added 28 commits May 6, 2020 17:20
I was trying to save area in the ProgRouter crossbar by sharing output queues between inter and intra FPGA links, but this introduces deadlock. Every trick I've tried to reduce area in the ProgRouter has met the same fate. So here's the fully parallel that's working very nicely so far, if a bit greedy in terms of FPGA area.
POLite now allows empty pins, so fan outs of some vertices may be zero
Multiple boxes in the Y direction only has stopped working.  Looking
back at the first commit the in 0.8 branch, it looks like I accidently
changed the behviour of inter-board routing by considering the host
bit before knowing that we're on the correct Y coordinate.  Hopefully,
this is the fix...
If POLITE_DUMP_STATS is defined then measuring time from the host
isn't very accurate because it will include the time to transfer a
large number of stats over the slow UART.  To help users become aware
of this, we now don't display the time if POLITE_DUMP_STATS is
enabled.
This is faster than METIS and gives similar results for a few graphs
that I've tried.  It works by picking an unvisited vertex, and then
doing a size-bounded BFS from that vertex with the size-bound equal
to the partition size.  This process is repeated until the partition
is full, at which point we move to a new parition and repeat the
process until all vertices have been visited.  It is just a few lines
of code, and could be easily parallelised in future.
Compiles but untested...
@mn416 mn416 merged commit d11655e into master Jun 24, 2020
coralmw pushed a commit that referenced this pull request Apr 26, 2022
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