rtl+sw: fix memory size constants

NikLeberg · Jan 1, 2024 · 69d7dc7 · 69d7dc7
1 parent 149049e
commit 69d7dc7
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Showing 3 changed files with 8 additions and 13 deletions.
diff --git a/scripts/makefile.def b/scripts/makefile.def
@@ -1,14 +1,8 @@
 # List of VHDL libraries.
 LIBS      ?= work    neorv32
 # List of paths to the corresponding libraries stated above.
-LIB_PATHS ?= ../vhdl ../lib/neorv32
+LIB_PATHS ?= ../vhdl ../lib/neorv32/rtl/core
 # Files to ignore in the above library paths.
-IGNORED_FILES += ../lib/neorv32/sim/simple/neorv32_imem.iram.simple.vhd
-IGNORED_FILES += ../lib/neorv32/sim/simple/neorv32_imem.simple.vhd
-IGNORED_FILES += ../lib/neorv32/sim/simple/neorv32_tb.simple.vhd
-IGNORED_FILES += ../lib/neorv32/sim/neorv32_tb.vhd
-IGNORED_FILES += ../lib/neorv32/sim/uart_rx_pkg.vhd
-IGNORED_FILES += ../lib/neorv32/sim/uart_rx.vhd
 IGNORED_FILES += ../lib/neorv32/rtl/core/mem/neorv32_imem.legacy.vhd
 IGNORED_FILES += ../lib/neorv32/rtl/core/mem/neorv32_dmem.legacy.vhd
 IGNORED_FILES += ../vhdl/vga/tb/vga_tb.vhdl

diff --git a/sw/makefile.sw b/sw/makefile.sw
@@ -9,7 +9,8 @@ MARCH = rv32ima_zicsr
 
 # User flags for additional configuration (will be added to compiler flags)
 USER_FLAGS := $(CLI_FLAGS)
-USER_FLAGS += -Wl,--defsym,__neorv32_ram_size=8k
+USER_FLAGS += -Wl,--defsym,__neorv32_rom_size=16K
+USER_FLAGS += -Wl,--defsym,__neorv32_ram_size=32M
 USER_FLAGS += -Og
 
 # Change flags if we are building for the sumulation.

diff --git a/vhdl/top/top.vhdl b/vhdl/top/top.vhdl
@@ -107,8 +107,8 @@ ARCHITECTURE top_arch OF top IS
     SIGNAL con_jtag_tck, con_jtag_tdi, con_jtag_tdo, con_jtag_tms : STD_LOGIC;
     SIGNAL con_gpio_o : STD_ULOGIC_VECTOR(63 DOWNTO 0);
     SIGNAL con_mti, con_msi : STD_ULOGIC_VECTOR(NUM_HARTS - 1 DOWNTO 0);
-    SIGNAL con_dci_ndmrstn : STD_ULOGIC;
-    SIGNAL con_dci_halt_req : STD_ULOGIC_VECTOR(NUM_HARTS - 1 DOWNTO 0);
+    SIGNAL con_dci_ndmrstn : STD_ULOGIC := '1';
+    SIGNAL con_dci_halt_req : STD_ULOGIC_VECTOR(NUM_HARTS - 1 DOWNTO 0) := (OTHERS => '0');
     SIGNAL con_dci_cpu_debug : STD_ULOGIC_VECTOR(NUM_HARTS - 1 DOWNTO 0);
 
     -- Wishbone interface signals
@@ -120,8 +120,8 @@ ARCHITECTURE top_arch OF top IS
     CONSTANT WB_N_SLAVES_MUX : NATURAL := 5;
     CONSTANT WB_MEMORY_MAP_CROSSBAR : wb_map_t :=
     (
-    (x"0000_0000", 1 * 1024), -- IMEM, 1 KB (port a)
-    (x"1000_0000", 1 * 1024), -- IMEM, 1 KB (port b)
+    (x"0000_0000", 16 * 1024), -- IMEM, 16 KB (port a)
+    (x"1000_0000", 16 * 1024), -- IMEM, 16 KB (port b)
     (x"8000_0000", 32 * 1024 * 1024) -- SDRAM, 32 MB
     );
     CONSTANT WB_MEMORY_MAP_MUX : wb_map_t :=
@@ -291,7 +291,7 @@ BEGIN
     gen_sim : IF SIMULATION = TRUE GENERATE
         wb_imem_inst : ENTITY work.wb_mem(simulation)
             GENERIC MAP(
-                MEM_SIZE  => 32 * 1024,             -- size of instruction memory in bytes
+                MEM_SIZE  => 16 * 1024,             -- size of instruction memory in bytes
                 MEM_IMAGE => application_init_image -- initialization image of memory
             )
             PORT MAP(