lib+rtl: update neorv32

NikLeberg · Jan 1, 2024 · 149049e · 149049e
1 parent 07820d5
commit 149049e
Show file tree

Hide file tree

Showing 7 changed files with 50 additions and 50 deletions.
diff --git a/lib/neorv32 b/lib/neorv32
diff --git a/vhdl/neorv32_cpu_smp/neorv32_cpu_smp.vhdl b/vhdl/neorv32_cpu_smp/neorv32_cpu_smp.vhdl
@@ -144,23 +144,24 @@ BEGIN
                 CPU_DEBUG_PARK_ADDR => dm_park_entry_c,                       -- cpu debug mode parking loop entry address
                 CPU_DEBUG_EXC_ADDR  => dm_exc_entry_c,                        -- cpu debug mode exception entry address
                 -- RISC-V CPU Extensions --
-                CPU_EXTENSION_RISCV_A        => true,                -- implement atomic memory operations extension?
-                CPU_EXTENSION_RISCV_B        => false,               -- implement bit-manipulation extension?
-                CPU_EXTENSION_RISCV_C        => false,               -- implement compressed extension?
-                CPU_EXTENSION_RISCV_E        => false,               -- implement embedded RF extension?
-                CPU_EXTENSION_RISCV_M        => true,                -- implement mul/div extension?
-                CPU_EXTENSION_RISCV_U        => false,               -- implement user mode extension?
-                CPU_EXTENSION_RISCV_Zfinx    => false,               -- implement 32-bit floating-point extension (using INT reg!)
-                CPU_EXTENSION_RISCV_Zicntr   => true,                -- implement base counters?
-                CPU_EXTENSION_RISCV_Zihpm    => false,               -- implement hardware performance monitors?
-                CPU_EXTENSION_RISCV_Zifencei => true,                -- implement instruction stream sync.?
-                CPU_EXTENSION_RISCV_Zmmul    => false,               -- implement multiply-only M sub-extension?
-                CPU_EXTENSION_RISCV_Zxcfu    => false,               -- implement custom (instr.) functions unit?
-                CPU_EXTENSION_RISCV_Sdext    => ON_CHIP_DEBUGGER_EN, -- implement external debug mode extension?
-                CPU_EXTENSION_RISCV_Sdtrig   => ON_CHIP_DEBUGGER_EN, -- implement debug mode trigger module extension?
+                CPU_EXTENSION_RISCV_A      => true,                -- implement atomic memory operations extension?
+                CPU_EXTENSION_RISCV_B      => false,               -- implement bit-manipulation extension?
+                CPU_EXTENSION_RISCV_C      => false,               -- implement compressed extension?
+                CPU_EXTENSION_RISCV_E      => false,               -- implement embedded RF extension?
+                CPU_EXTENSION_RISCV_M      => true,                -- implement mul/div extension?
+                CPU_EXTENSION_RISCV_U      => false,               -- implement user mode extension?
+                CPU_EXTENSION_RISCV_Zfinx  => false,               -- implement 32-bit floating-point extension (using INT reg!)
+                CPU_EXTENSION_RISCV_Zicntr => true,                -- implement base counters?
+                CPU_EXTENSION_RISCV_Zicond => false,               -- implement integer conditional operations?
+                CPU_EXTENSION_RISCV_Zihpm  => false,               -- implement hardware performance monitors?
+                CPU_EXTENSION_RISCV_Zmmul  => false,               -- implement multiply-only M sub-extension?
+                CPU_EXTENSION_RISCV_Zxcfu  => false,               -- implement custom (instr.) functions unit?
+                CPU_EXTENSION_RISCV_Sdext  => ON_CHIP_DEBUGGER_EN, -- implement external debug mode extension?
+                CPU_EXTENSION_RISCV_Sdtrig => ON_CHIP_DEBUGGER_EN, -- implement debug mode trigger module extension?
                 -- Extension Options --
-                FAST_MUL_EN   => true,  -- use DSPs for M extension's multiplier
-                FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
+                FAST_MUL_EN    => true,  -- use DSPs for M extension's multiplier
+                FAST_SHIFT_EN  => false, -- use barrel shifter for shift operations
+                REGFILE_HW_RST => false, -- implement full hardware reset for register file
                 -- Physical Memory Protection (PMP) --
                 PMP_NUM_REGIONS     => 0, -- number of regions (0..16)
                 PMP_MIN_GRANULARITY => 4, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes

diff --git a/vhdl/neorv32_debug/neorv32_debug.vhdl b/vhdl/neorv32_debug/neorv32_debug.vhdl
@@ -67,8 +67,8 @@ ARCHITECTURE no_target_specific OF neorv32_debug IS
 BEGIN
 
     -- Map Wishbone signals to neorv32 internal bus.
-    req.we <= wb_slave_i.stb AND wb_slave_i.we;
-    req.re <= wb_slave_i.stb AND NOT wb_slave_i.we;
+    req.stb <= wb_slave_i.stb;
+    req.rw <= wb_slave_i.we;
     req.addr <= wb_slave_i.adr;
     req.data <= wb_slave_i.dat;
     req.ben <= wb_slave_i.sel;

diff --git a/vhdl/neorv32_debug/neorv32_debug_dm_smp.vhd b/vhdl/neorv32_debug/neorv32_debug_dm_smp.vhd
@@ -728,8 +728,8 @@ begin
 
   -- Access Control ------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  rden <= or_reduce_f(cpu_debug_i) and bus_req_i.re; -- allow access only when in debug mode
-  wren <= or_reduce_f(cpu_debug_i) and bus_req_i.we; -- allow access only when in debug mode
+  rden <= or_reduce_f(cpu_debug_i) and bus_req_i.stb and not bus_req_i.rw; -- allow access only when in debug mode
+  wren <= or_reduce_f(cpu_debug_i) and bus_req_i.stb and     bus_req_i.rw; -- allow access only when in debug mode
 
 
   -- Write Access ---------------------------------------------------------------------------

diff --git a/vhdl/neorv32_debug/tb/neorv32_debug_dm_smp_tb.vhdl b/vhdl/neorv32_debug/tb/neorv32_debug_dm_smp_tb.vhdl
@@ -178,8 +178,8 @@ BEGIN
         );
 
     -- Map Wishbone signals to neorv32 internal bus of debug module.
-    bus_req.we <= wb_slv_req(1).stb AND wb_slv_req(1).we;
-    bus_req.re <= wb_slv_req(1).stb AND NOT wb_slv_req(1).we;
+    bus_req.stb <= wb_slv_req(1).stb;
+    bus_req.rw <= wb_slv_req(1).we;
     bus_req.addr <= wb_slv_req(1).adr;
     bus_req.data <= wb_slv_req(1).dat;
     bus_req.ben <= wb_slv_req(1).sel;

diff --git a/vhdl/neorv32_wb_io/neorv32_wb_gateway.vhdl b/vhdl/neorv32_wb_io/neorv32_wb_gateway.vhdl
@@ -3,7 +3,7 @@
 --
 -- Authors:                 Niklaus Leuenberger <[email protected]>
 --
--- Version:                 0.3
+-- Version:                 0.4
 --
 -- Entity:                  neorv32_wb_gateway
 --
@@ -17,6 +17,8 @@
 --                              allow bus to be locked by lr/sc atomic ops
 --                          0.3, 2023-09-30, leuen4
 --                              reduce latency, immediately forward request
+--                          0.4, 2024-01-01, leuen4
+--                              update to new neorv32 stb and rw bus signals
 -- =============================================================================
 
 LIBRARY ieee;
@@ -46,54 +48,51 @@ END ENTITY neorv32_wb_gateway;
 
 ARCHITECTURE no_target_specific OF neorv32_wb_gateway IS
 
-    -- Register for pending bus access (rden_i or wren_i was asserted).
-    SIGNAL pending_read : STD_ULOGIC; -- set on read request
-    SIGNAL pending_write : STD_ULOGIC; -- set on write request
+    -- Registers for bus access state.
+    SIGNAL pending_request : STD_ULOGIC; -- a request is pending
     SIGNAL pending_atomic : STD_ULOGIC; -- lr/sc pair in progress
-    SIGNAL active_request : STD_ULOGIC; -- a request is currently active
+    SIGNAL active_request : STD_ULOGIC; -- a request is currently in progress
 
 BEGIN
 
-    -- CPU specific bus asserts rden_i and wren_i for one clock only. Wishbone
-    -- requires cyc & stb signals to be active for the whole transaction. Safe
-    -- the pending state of an access and output that as cyc signal. 
+    -- CPU specific bus asserts stb_i for one clock only. Wishbone requires cyc
+    -- & stb signals to be active for the whole transaction. Safe the pending
+    -- state of an access and output that as cyc signal. 
     proc_request : PROCESS (clk_i) IS
     BEGIN
         IF rising_edge(clk_i) THEN
             IF rstn_i = '0' THEN
-                pending_read <= '0';
-                pending_write <= '0';
+                pending_request <= '0';
                 pending_atomic <= '0';
             ELSE
-                -- Start a request on either re or we assertion. Request is
-                -- pending until either ack or err was returned.
-                IF req_i.re = '1' THEN
-                    pending_read <= '1';
-                ELSIF req_i.we = '1' THEN
-                    pending_write <= '1';
+                -- Start a request on stb assertion. Request is pending until
+                -- either ack or err was returned.
+                IF req_i.stb = '1' THEN
+                    pending_request <= '1';
                 ELSIF (wb_master_i.ack OR wb_master_i.err) = '1' THEN
-                    pending_read <= '0';
-                    pending_write <= '0';
+                    pending_request <= '0';
                 END IF;
-                -- Mark request as atomic read/write pair if rvso bit is set.
-                -- Atomic request is reset on next re or we assertion.
-                IF pending_atomic = '0' AND (req_i.re AND req_i.rvso) = '1' THEN
+                -- Lock on to slave during atomic read/write access from lr/sc
+                -- instruction pairs. Mark current req only as atomic if its a
+                -- lr (rvso = 1, rw = 0). Otherwise a spurious single sc would
+                -- lock the bus. Atomic request is reset on next stb assertion.
+                IF pending_atomic = '0' AND (req_i.stb AND (NOT req_i.rw) AND req_i.rvso) = '1' THEN
                     pending_atomic <= '1';
-                ELSIF pending_atomic = '1' AND (req_i.re OR req_i.we) = '1' THEN
+                ELSIF pending_atomic = '1' AND req_i.stb = '1' THEN
                     pending_atomic <= '0';
                 END IF;
             END IF;
         END IF;
     END PROCESS proc_request;
 
-    -- A request of active if the current cycle has a request, or a previous
+    -- A request is active if the current cycle has a strobe, or a previous
     -- request was not fullfulled yet.
-    active_request <= req_i.re OR req_i.we OR pending_read OR pending_write;
+    active_request <= req_i.stb OR pending_request;
 
     -- Map CPU bus to Wishbone.
     wb_master_o.cyc <= active_request OR pending_atomic; -- hold on to slave if atomic access
     wb_master_o.stb <= active_request;
-    wb_master_o.we <= pending_write;
+    wb_master_o.we <= req_i.rw;
     wb_master_o.sel <= req_i.ben;
     wb_master_o.adr <= req_i.addr;
     wb_master_o.dat <= req_i.data;

diff --git a/vhdl/neorv32_wb_io/neorv32_wb_gpio.vhdl b/vhdl/neorv32_wb_io/neorv32_wb_gpio.vhdl
@@ -57,8 +57,8 @@ ARCHITECTURE no_target_specific OF neorv32_wb_gpio IS
 BEGIN
 
     -- Map Wishbone signals to neorv32 internal bus.
-    req.we <= wb_slave_i.stb AND wb_slave_i.we;
-    req.re <= wb_slave_i.stb AND NOT wb_slave_i.we;
+    req.stb <= wb_slave_i.stb;
+    req.rw <= wb_slave_i.we;
     req.addr <= wb_slave_i.adr;
     req.data <= wb_slave_i.dat;
     wb_slave_o.dat <= rsp.data;