Add new execution mode to SPV_INTEL_kernel_attributes#176
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johnkslang merged 2 commits intoKhronosGroup:mainfrom Feb 15, 2023
Merged
Add new execution mode to SPV_INTEL_kernel_attributes#176johnkslang merged 2 commits intoKhronosGroup:mainfrom
johnkslang merged 2 commits intoKhronosGroup:mainfrom
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The html file was updated using the VSCode AsciiDoc extension. |
This was referenced Dec 8, 2022
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Please take a look, @johnkslang / @alan-baker , thank you! |
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Can you please add a link to this extension in the README also? |
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The readme already seems to have this extension linked since it's an existing extension. |
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ping @bashbaug , @johnkslang (I am unable add you as git reviewers) |
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The readme already seems to have this extension linked since it's an existing extension.
Whoops, I'd missed that, sorry!
LGTM, needs a non-Intel reviewer before merging.
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ping @johnkslang / @dneto0 / @alan-baker for review. Thank you! |
MrSidims
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Mar 8, 2023
This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels. The RegisterMapInterfaceINTEL execution mode is added with a 0/1 literal based on the kernel metadata. When the metadata is: !ip_interface !N !N = !{!"csr"} The translator emits RegisterMapInterfaceINTEL 0, and when the metadata is: !ip_interface !N !N = !{!"csr", !"accept_downstream_stall"} The translator emits RegisterMapInterfaceINTEL 1 NOTE The new mode is under capability FPGAKernelAttributesv2INTEL which implicitly defines the capability FPGAKernelAttributesv2INTEL. This PR is very similar to Implement StreamingInterfaceINTEL execution mode #1218
FreddyLeaf
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This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels. The RegisterMapInterfaceINTEL execution mode is added with a 0/1 literal based on the kernel metadata. When the metadata is: !ip_interface !N !N = !{!"csr"} The translator emits RegisterMapInterfaceINTEL 0, and when the metadata is: !ip_interface !N !N = !{!"csr", !"accept_downstream_stall"} The translator emits RegisterMapInterfaceINTEL 1 NOTE The new mode is under capability FPGAKernelAttributesv2INTEL which implicitly defines the capability FPGAKernelAttributesv2INTEL. This PR is very similar to Implement StreamingInterfaceINTEL execution mode intel#1218 Original commit: KhronosGroup/SPIRV-LLVM-Translator@a9f4f25
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…ution mode This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels.
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…ution mode This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels.
MrSidims
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Feb 28, 2024
* Backport from llvm16 branch: Support FPGA function !spirv.Decoration metadata Supporting the new FPGA kernel attribute pipelined needs the translator to handle !spirv.Decoration metadata on functions as well as on global variables. If the MD is found on the function, call the existing translation of metadata. * Backport from llvm16 branch: Implement RegisterMapInterfaceINTEL execution mode This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels. * Backport from llvm16 branch: Implement SPIR-V support for max_reinvocation_delay attribute The attribute generates the llvm.loop.intel.max_reinvocation_delay.count metadata in LLVM IR. There is one positive integer literal operand denoting the maximum number of cycles allowed between loop invocations. * Backport from llvm18 branch: Support sycl_ext_oneapi_prefetch Handle new properties and decorate prefetch's arg.
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FPGA kernels can have two types of interfaces - streaming based or register based. This PR adds a new execution mode (
RegisterMapInterfaceINTEL) which specifies a 'register' based interface.RegisterMapInterfaceINTELis being added to the existingSPV_INTEL_kernel_attributesextension as this extension already has the other execution mode (StreamingInterfaceINTEL) that represents the streaming based interface. We want to keep these two related modes together in one extension document.To allow backwards compatibility, the new mode is guarded by a new capability
FPGAKernelAttributesv2INTEL.