Backport of Implementation of vector compute extension #582
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- Refactored --spirv-ocl-builtins-version option so it can be set via library interface as well. - Removed logic that relied on OpSource while generating LLVM IR for OpenCL built-in functions - Added one more library entry entry point: 'convertSpirvToLLVM' which is a copy of existing one, but accept TranslatorOpts argument
- renamed "spirv-ocl-builtins-version" to "spirv-target-env" - adjusted tests
Here is implementation of command-line option which will allow to represent unknown llvm intrinsics as external function call in SPIR-V Change-Id: I194bcd937d02112d51851a4808fd15bab2d1ba3a Signed-off-by: Ilya Mashkov <[email protected]>
* Fix CapabilitySubgroupDispatch name in SPIRVNameMapEnum.h * Add ExecutionModeSubgroupSize to SPIRVNameMapEnum.h Change-Id: Iee705ff82fd68dab6a543276fa02ced035e7b585
Change-Id: Id91acff717f8754825cef2c3dffe78327a8beb74
Change-Id: Ie8b9d3cbbf80d13d7b7f93f2c89424b23b90077d
Change-Id: I4292aa2126a11986958f15afd8dddfe73eaae249
Added support for `SPV_KHR_float_controls` extension to SPIR-V generator part Fixed not emitting required extensions for capabilities Change-Id: If71942c556fd0f315b3e6181bd1bc4e7552403e5
* Refined condition for CapabilityVector16 * Removed redundant assert from SPIRVVectorShuffle This assert is redundant because the allowed size of Components is checked by Type. Moreover it can interfere with capabilities allowing non-standart sizes. * Added required capabilities for ExecutionModeSubgroupSize * Added missing float control capabilities to SPIRVIsValidEnum.h Change-Id: I6f21f2375d4d905a181098dfb539fe162f9b1f95
Extension is published at intel/llvm#1611 Change-Id: I8e67d12a776e4843f724ed1111c29022af2fed6a
Extension is published at intel/llvm#1612 Change-Id: I145ca21c3f99ec11cfe0c4758e205564af5cff6f Co-Authored-By: Aleksandr Bezzubikov <[email protected]> Co-Authored-By: Aleksander Us <[email protected]> Co-Authored-By: Alexey Sachkov <[email protected]> Co-Authored-By: Alexey Sotkin <[email protected]> Co-Authored-By: Anton Sidorenko <[email protected]> Co-Authored-By: Gang Chen <[email protected]> Co-Authored-By: Kai Chen <[email protected]> Co-Authored-By: Konstantin Vladimirov <[email protected]> Co-Authored-By: Wei Pan <[email protected]>
Extension is published at intel/llvm#1612 Change-Id: I41a57cd0c935d227dc1d0b5d7d0cbeb655589a8c Co-Authored-By: Aleksandr Bezzubikov <[email protected]> Co-Authored-By: Aleksander Us <[email protected]> Co-Authored-By: Alexey Sachkov <[email protected]> Co-Authored-By: Alexey Sotkin <[email protected]> Co-Authored-By: Anton Sidorenko <[email protected]> Co-Authored-By: Gang Chen <[email protected]> Co-Authored-By: Kai Chen <[email protected]> Co-Authored-By: Konstantin Vladimirov <[email protected]> Co-Authored-By: Wei Pan <[email protected]>
Extension is published at intel/llvm#1612 Change-Id: Ia701c92c248034fd26ae8ed425ac70571a51eace Co-Authored-By: Aleksandr Bezzubikov <[email protected]> Co-Authored-By: Aleksander Us <[email protected]> Co-Authored-By: Alexey Sachkov <[email protected]> Co-Authored-By: Alexey Sotkin <[email protected]> Co-Authored-By: Anton Sidorenko <[email protected]> Co-Authored-By: Gang Chen <[email protected]> Co-Authored-By: Kai Chen <[email protected]> Co-Authored-By: Konstantin Vladimirov <[email protected]> Co-Authored-By: Wei Pan <[email protected]>
SPV_INTEL_float_controls2 and SPV_KHR_float_controls extensions Extensions are published at intel/llvm#1612 intel/llvm#1611
AlexeySotkin
approved these changes
Jun 26, 2020
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Extensions are published at intel/llvm#1612 and intel/llvm#1611
Also, backport of other commits needed for vector compute