channels: fix memory ordering violation in iterate #52407
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Channel `iterate` calls might miss trailing items without this patch. I have not seen proof of this reaching a failure, but we do appear to be missing this ordering specification in visual review. Should not make a difference to generated code on x86, which already has TSO guaranteed, but may alter optimizations and other CPUs with weaker memory orderings.
vtjnash
added
backport 1.9
gbaraldi
approved these changes
Dec 5, 2023
KristofferC
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that referenced
this pull request
Dec 12, 2023
Channel `iterate` calls might miss trailing items without this patch. I have not seen proof of this reaching a failure, but we do appear to be missing this ordering specification in visual review. Should not make a difference to generated code on x86, which already has TSO guaranteed, but may alter optimizations and other CPUs with weaker memory orderings. (cherry picked from commit 856e112)
KristofferC
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that referenced
this pull request
Dec 17, 2023
Backported PRs: - [x] #51234 <!-- Fix getfield codegen for tuple inputs and unknown symbol fields. --> - [x] #52170 <!-- fix invalidations related to `ismutable` --> - [x] #52342 <!-- Add single-term multiplication for `AbstractQ` on v1.10 and above --> - [x] #52333 <!-- bugfix for dot of Hermitian{noncommutative} --> - [x] #52407 <!-- channels: fix memory ordering violation in iterate --> - [x] #52405 <!-- Bump LLVM to 15.0.7+10 to fix GC issue --> - [x] #52441 <!-- Remove `Pkg` dependency from `SuiteSparse_jll` --> - [x] #52367 <!-- docs: add notes about scratchspaces in depot --> - [x] #52456 <!-- Make `jl_write_coverage_data` dllexported again --> - [x] #52294 <!-- GC scheduler refinements --> - [x] #52359 <!-- make custom log macros work --> - [x] #52548
KristofferC
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the
backport 1.10
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Channel
iteratecalls might miss trailing items without this patch. I have not seen proof of this reaching a failure, but we do appear to be missing this ordering specification in visual review.Should not make a difference to generated code on x86, which already has TSO guaranteed, but may alter optimizations and other CPUs with weaker memory orderings.