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Allow slashes in write_aig_external filenames #1443

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Sep 1, 2021
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Allow slashes in write_aig_external filenames #1443

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8 changes: 4 additions & 4 deletions intTests/test_external_abc/test.saw
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Expand Up @@ -16,16 +16,16 @@ let q_unsat = {{ \(x:[8]) -> x != 0 /\ x+x == x }};

write_verilog "write_verilog_unsat.v" q_unsat;
write_smtlib2_w4 "write_smtlib2_w4_unsat.smt2" q_unsat;
write_aig_external "write_aig_external_unsat.aig" q_unsat;
write_cnf_external "write_aig_external_unsat.cnf" q_unsat;
write_aig_external "./write_aig_external_unsat.aig" q_unsat;
write_cnf_external "./write_aig_external_unsat.cnf" q_unsat;
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Just to be clear: The ./ part is not suddenly required now, is it? You've just added it in this test case to exercise the new takeBaseName functionality, because the ./ prefix wouldn't have worked before?

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Yes, exactly. It most certainly is not required, but this approach seemed like an easy way to make sure it was working.


// A formula that is satisfiable.
let q_sat = {{ \(x:[8]) -> x+x == x }};

write_verilog "write_verilog_sat.v" q_sat;
write_smtlib2_w4 "write_smtlib2_w4_sat.smt2" q_sat;
write_aig_external "write_aig_external_sat.aig" q_sat;
write_cnf_external "write_aig_external_sat.cnf" q_sat;
write_aig_external "./write_aig_external_sat.aig" q_sat;
write_cnf_external "./write_aig_external_sat.cnf" q_sat;

fails (prove_print sbv_abc q_sat);
fails (prove_print w4_abc_smtlib2 q_sat);
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5 changes: 3 additions & 2 deletions src/SAWScript/Prover/Exporter.hs
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Expand Up @@ -56,6 +56,7 @@ import qualified Data.Map as Map
import Data.Set (Set)
import qualified Data.SBV.Dynamic as SBV
import System.Directory (removeFile)
import System.FilePath (takeBaseName)
import System.IO
import System.IO.Temp(emptySystemTempFile)
import Data.Text (pack)
Expand Down Expand Up @@ -148,8 +149,8 @@ writeAIG f t = do
io $ AIG.writeAiger f aig

withABCVerilog :: FilePath -> Term -> (FilePath -> String) -> TopLevel ()
withABCVerilog baseName t buildCmd =
do verilogFile <- io $ emptySystemTempFile (baseName ++ ".v")
withABCVerilog fileName t buildCmd =
do verilogFile <- io $ emptySystemTempFile (takeBaseName fileName ++ ".v")
sc <- getSharedContext
write_verilog sc verilogFile t
io $
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