[ROCm][MiniMax-M3] Support an fp8 indexer KV cache

[Fangzhou-Ai]

Purpose

Enable --attention-config '{"indexer_kv_dtype":"fp8"}' on the ROCm/AMD MiniMax-M3
path. The AMD sparse-attention layer never read attention_config.indexer_kv_dtype, so
the indexer side cache was bf16 unconditionally.

Four one-to-ten-line changes:

file	change	why
amd/ops/index_topk.py	tl.dot(q, k.to(q.dtype), out_dtype=tl.float32) in the prefill scorer, tl.dot(k.to(q.dtype), q, ...) in the decode scorer	tl.dot needs matching operand dtypes; there is no fp8×bf16 MMA, so an e4m3 cache must be widened to the query dtype. Folds to a no-op for a bf16 cache — existing behavior is bit-identical. Also compiles on Triton front-ends that reject fp8 dot operands outright (Unsupported lhs dtype fp8e4nv).
amd/ops/sparse_pa.py	value.to(dst.dtype.element_ty) on the side-cache store	the side cache may be e4m3 while the index keys arriving are bf16
amd/model.py	read indexer_kv_dtype from attention_config, pass it to MiniMaxM3Indexer, reject the unsupported combination	the plumbing that was missing
common/indexer.py	relax the Triton-impl dtype guard to accept fp8/fp8_e4m3	see "Relationship to vllm-project#47665" below

Why fp8 helps

The indexer's decode cost is dominated by re-reading its per-token index-K side cache
every step across all sparse layers, and the scorer is DRAM-bandwidth-bound. e4m3 halves
that read and the side cache's share of the KV pool. The scores only feed a top-k block
ranking — attention itself still reads the main KV cache at full precision.

Why this needs the AITER sparse-PA path

VLLM_ROCM_SHUFFLE_KV_CACHE_LAYOUT=1 is currently mandatory, but not because the
fused insert kernel lacks fp8 support -- it has it
(csrc/libtorch_stable/fused_minimax_m3_qknorm_rope_kv_insert_kernel.cu: "Indexer
index-K cache: independent dtype -- qkv dtype or fp8 e4m3", with a storeElemsFp8
store path).

The actual constraint is that the kernel requires both index outputs to agree:

// fp8 index path: ... Both index outputs must agree.
STD_TORCH_CHECK(!index_q_out.has_value() || index_q_out->scalar_type() == kFp8,
                "fp8 index path: index_q_out must be fp8 e4m3");

The non-sparse path allocates index_q = qkv.new_empty(...) in qkv dtype (bf16), so an
fp8 index cache trips that check. On the sparse-PA path the fused op runs in norm+rope
mode only (no kv_cache/index_cache passed), and the side cache is written by the
separate Triton insert this PR makes dtype-agnostic -- so there is no such coupling.

Lifting the requirement is follow-on work in this same model: allocate index_q as fp8
and let the Triton score kernels take an fp8 query. Worth doing, because forcing the
sparse-PA path is what costs low-concurrency throughput. Until then the layer raises on
the unsupported combination rather than silently keeping bf16 keys.

Note this is a genuine user-facing trade (see accuracy below), which is why it stays
opt-in behind the existing attention_config field rather than becoming the default.

Relationship to vllm-project#47665

vllm-project#47665 (open, by @jarrelscy) does the same thing for the non-SM100 CUDA path and does
not enable ROCm. vllm/models/minimax_m3/amd/ops/index_topk.py is a separate fork of
common/ops/index_topk.py; vllm-project#47665 only patches the common/ copy, and neither the AMD
side-cache insert nor the AMD attention-layer plumbing exists there.

The one line that does overlap is the dtype guard in common/indexer.py. This PR keeps
it so it works standalone; if vllm-project#47665 lands first I will drop that hunk on rebase.
Whichever merges second just rebases.

Test Plan and Result

MiniMax-M3-MXFP4, MI355X, TP4, 8k/1k ISL/OSL, spec-none, one sample per point.

Base: vLLM at the Docker build commit with VLLM_ROCM_SHUFFLE_KV_CACHE_LAYOUT=1 and
nothing else -- no online-quant overlay, no fusions, no tuned MoE config. Both arms run
sparse PA, so this isolates the indexer dtype alone; it does not include the cost of
enabling sparse PA in the first place, which is a separate decision.

conc	bf16 indexer	fp8 indexer		TPOT bf16 -> fp8
4	4,060	4,074	+0.4%	8.38 -> 8.35 ms
8	6,765	6,806	+0.6%	10.02 -> 9.95 ms
64	22,044	22,595	+2.5%	24.83 -> 24.19 ms
128	27,778	28,667	+3.2%	39.52 -> 38.23 ms

The gain rises monotonically with concurrency, which is the expected signature: the
index-cache read scales with batch x context, so halving it pays more as both grow. No
concurrency regresses.

One effect is bundled into these numbers. With an fp8 side cache the KV cache becomes
single-precision, so needs_kv_cache_zeroing is False and per-step block zeroing is
skipped entirely; the bf16 arm is mixed-precision and pays it. Some unknown share of the
gain above is that, not a faster index scan. Separating them would need a build with
zeroing forced on, which was not run. The combined effect is what a deployment actually
gets from flipping this flag on an fp8-KV-cache config.

Accuracy (GSM8K 5-shot, n=1319, stderr ~0.006): strict 0.9416 / flexible 0.9409.
A same-stack bf16-indexer control measured 0.9530 / 0.9522 — but that is ~1.3σ unpaired,
and a later rebuild of the stack with the bf16 indexer moved GSM8K by only +0.15 pt while
costing 2.2% at c64. So I would not claim a measured accuracy cost here; treat it as
unresolved. Every config measured sat at ~0.94 ± 0.01.

Mechanism if real: fp8 index keys perturb block ordering near score ties, so sparse
attention reads a slightly different block set.

Lint: ruff check and ruff format --check (v0.14.0, as pinned in
.pre-commit-config.yaml) clean. pre-commit itself could not run — no pre_commit
module in the venv — so the hooks were run manually.

No unit test added: the AMD kernel paths need a ROCm runner. vllm-project#47665 adds a
platform-agnostic fp8-vs-bf16 top-k agreement test that would cover the shared guard.

Duplicate check

gh pr list --repo vllm-project/vllm --state open --search over "minimax indexer",
"indexer_kv_dtype", "minimax_m3 fp8", "minimax m3 rocm", "sparse pa aiter minimax".
Only vllm-project#47665 overlaps, discussed above. vllm-project#49199 also touches amd/ops/index_topk.py, so a
small conflict there is possible.

Notes

AI assistance (Claude Code) was used for this change.

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