Ifu cache update

source/IDU/IDU.sv

@@ -0,0 +1,67 @@
+module idu (
+    input logic [31:0] instr1,       
+    input logic [31:0] instr2,      
+    output logic [31:0] issue_instr1, // Instruction for primary issue
+    output logic [31:0] issue_instr2  // Instruction for secondary issue
+);
+
+    // Dependency Flags
+    logic raw_dependency;  // Read-After-Write (RAW)
+    logic waw_dependency;  // Write-After-Write (WAW)
+    logic branch_instr;    // Branch detection
+    logic mem_access_instr1; // Memory access detection for instr1
+    logic mem_access_instr2; // Memory access detection for instr2
+
+
+
+    logic [6:0] opcode1, opcode2;    // Opcode fields for instr1 and instr2
+    logic [4:0] rd1, rs1_1, rs2_1;  // Fields for instr1
+    logic [4:0] rd2, rs1_2, rs2_2;  // Fields for instr2
+
+    assign opcode1 = instr1[6:0];
+    assign opcode2 = instr2[6:0];
+
+    assign rd1 = instr1[11:7];
+    assign rs1_1 = instr1[19:15];
+    assign rs2_1 = instr1[24:20];
+
+    assign rd2 = instr2[11:7];
+    assign rs1_2 = instr2[19:15];
+    assign rs2_2 = instr2[24:20];
+
+
+    assign raw_dependency = (rs1_2 == rd1) || (rs2_2 == rd1);
+
+    assign waw_dependency = (rd1 == rd2) && (rd1 != 5'b0);
+
+    // Branch Detection
+    assign branch_instr = (opcode1 == 7'b1100011); 
+
+    // Memory Access Detection
+    assign mem_access_instr1 = (opcode1 == 7'b0000011) || // Load instructions
+                               (opcode1 == 7'b0100011);  // Store instructions
+
+    assign mem_access_instr2 = (opcode2 == 7'b0000011) || // Load instructions
+                               (opcode2 == 7'b0100011);  // Store instructions
+
+
+
+
+    always_comb begin
+        // Default assignments
+        issue_instr1 = instr1;     
+        issue_instr2 = instr2;     
+
+        // Ensure memory access in primary issue
+        if (mem_access_instr2 && mem_access_instr1 == 0) begin
+            issue_instr1 = instr2;
+            issue_instr2 = instr1;
+        end
+
+        // Stall the second pipe if there are dependencies, branch, or memory access
+        if (raw_dependency || waw_dependency || branch_instr || mem_access_instr2) begin
+            issue_instr2 = 32'b0; 
+        end
+    end
+
+endmodule

source/IDU/IDU_rtl_list.f

@@ -0,0 +1,5 @@
+
++incdir+../../../source/common/
+
+//RTL FIle
+../../../source/idu/idu.sv

source/ifu/ifu.sv

@@ -0,0 +1,137 @@
+`include "macros.vh"
+
+module ifu
+import ifu_pkg::*;
+(
+    // Chip Signals
+    input logic Clock,
+    input logic Rst,
+
+    // CPU Interface
+    input logic [ADDR_WIDTH-1:0] cpu_reqAddrIn,         // Address requested by the CPU
+    output logic [ADDR_WIDTH-1:0] cpu_rspAddrOut,       // Address of the line in the response to CPU 
+    output logic [LINE_WIDTH-1:0] cpu_rspInsLineOut,    // Instruction line in the response to CPU
+    output logic cpu_rspInsLineValidOut,                // Indicates if the response is valid
+
+    // Memory Interface
+    input logic [TAG_WIDTH-1:0] mem_rspTagIn,       // Tag of the line provided by memory
+    input logic [LINE_WIDTH-1:0] mem_rspInsLineIn,  // Line data provided by memory
+    input logic mem_rspInsLineValidIn,              // Valid signal for memory response
+    output logic [ADDR_WIDTH-1:0] mem_reqTagOut,    // Indicates if memory is ready for requests
+    output logic mem_reqTagValidOut                    // Indicates if a memory request is valid
+);
+
+
+///////////////////
+// Logic Defines //
+///////////////////
+// data insertion
+logic insertionOnMiss;
+logic insertionOnPrefetch;
+logic p_reqSent;
+
+// cache signals
+logic [TAG_WIDTH - 1: 0] c_mem_reqTagOut;
+logic c_mem_reqTagValidOut;
+
+// prefetcher signals
+logic [TAG_WIDTH - 1: 0] p_mem_reqTagOut;
+logic p_mem_reqTagValidOut;
+
+// cache <-> prefetcher 
+logic                    c2p_rspTagValid; 
+logic                    c2p_rspTagStatus;
+logic [TAG_WIDTH - 1: 0] c2p_rspTag;
+logic                    p2c_reqTagValid;
+logic [TAG_WIDTH - 1: 0] p2c_reqTag;
+
+///////////
+// Cache //
+///////////
+ifu_cache ifu_cache (
+    .Clock(Clock),                                          // Input
+    .Rst(Rst),                                              // Input
+
+    // Prefetcher Interface
+    .pref_reqTagValidIn(p2c_reqTag),                        // Input
+    .pref_reqTagIn(p2c_reqTagValid),                        // Input
+    .pref_rspTagValidOut(c2p_rspTagValid),                  // Output
+    .pref_rspTagStatusOut(c2p_rspTagStatus),                // Output
+    .pref_rspTagOut(p2c_reqTag),                            // Output
+
+    // CPU Interface
+    .cpu_reqAddrIn(cpu_reqAddrIn),                          // Input
+    .cpu_rspAddrOut(cpu_rspAddrOut),                        // Output
+    .cpu_rspInsLineOut(cpu_rspInsLineOut),                  // Output
+    .cpu_rspInsLineValidOut(cpu_rspInsLineValidOut),        // Output
+
+    // Memory Interface
+    .mem_rspTagIn(mem_rspTagIn),                            // Input
+    .mem_rspInsLineIn(mem_rspInsLineIn),                    // Input
+    .mem_rspInsLineValidIn(mem_rspInsLineValidIn),          // Input
+    .mem_reqTagOut(c_mem_reqTagOut),                        // Output
+    .mem_reqTagValidOut(c_mem_reqTagValidOut)               // Output
+);
+
+////////////////
+// Prefetcher //
+////////////////
+ifu_prefetcher ifu_prefetcher (
+    .Clock(Clock),                                          // Input
+    .Rst(Rst),                                              // Input
+
+    // Cache Interface
+    .cache_rspTagValidIn(c2p_rspTagValid),                  // input
+    .cache_rspTagStatusIn(c2p_rspTagStatus),                // input
+    .cache_rspTagIn(c2p_rspTag),                            // input
+    .cache_reqTagValidOut(p2c_reqTagValid),                 // Output 
+    .cache_reqTagOut(p2c_reqTag),                           // Output 
+
+    // IFU signals
+    .ifu_prefReqSent(p_reqSent),                            // Input
+
+    // CPU Interface
+    .cpu_reqAddrIn(cpu_reqAddrIn),                          // Input
+
+    // Memory Interface
+    .mem_rspTagIn(mem_rspTagIn),                            // input
+    .mem_rspInsLineValidIn(mem_rspInsLineValidIn),          // input
+    .mem_reqTagOut(p_mem_reqTagOut),                        // Output  
+    .mem_reqTagValidOut(p_mem_reqTagValidOut)               // Output
+);
+
+
+/////////////
+// Assigns //
+/////////////
+assign insertionOnMiss = (c_mem_reqTagValidOut == VALID) && (mem_rspInsLineValidIn == VALID) && (c_mem_reqTagOut == mem_rspTagIn);
+assign insertionOnPrefetch = (mem_rspInsLineValidIn == VALID) && (p_mem_reqTagValidOut == !VALID) && !insertionOnMiss;
+
+
+///////////////////////////
+// Always Comb Statement //
+///////////////////////////
+always_comb begin
+
+    if (insertionOnMiss) begin
+        mem_reqTagOut = c_mem_reqTagOut;
+    end 
+
+    if (insertionOnPrefetch) begin
+        mem_reqTagOut = p_mem_reqTagOut;
+        p_reqSent = VALID;
+    end
+
+    if (insertionOnMiss || insertionOnPrefetch) begin
+        mem_reqTagValidOut = VALID;
+    end
+
+end
+
+///////////////////////////
+// Always_FF Statement //
+///////////////////////////
+
+
+endmodule
+