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25 Open 276 Closed
25 Open 276 Closed
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Issues list

Design single cycle RV32I core Learning Learning RTL design SC_CORE verificaiton
#773 opened Dec 28, 2024 by roman012285 MAFIA 2.3
@zenabiadsy @ObaidaM2912
Design simple riscv32I single cylce core Learning Learning RTL design
#772 opened Dec 25, 2024 by roman012285
@orengold7 @Danytartak
Complete the design of IFU unit big_core CACHE_MEM RTL design verificaiton
#771 opened Dec 24, 2024 by roman012285
@roman012285
Review this github repository, and improve the README file under the source directory
#761 opened Dec 5, 2024 by amichai-bd
1
Design of IFU unit big_core build & env
#757 opened Dec 3, 2024 by roman012285
7 tasks
MAFIA 2.1
2
@abdkeb @muhammad3mar
Add valid bit for big_core-mem_ss interface big_core CACHE_MEM
#741 opened Oct 28, 2024 by amichai-bd
@amichai-bd
Create big_cores fabric build & env FABRIC
#696 opened Jun 29, 2024 by roman012285 MAFIA 1.1
@roman012285
Design mem_ss to work with SDRAM controller and D_CACHE big_core CACHE_MEM FPGA
#639 opened May 10, 2024 by roman012285 MAFIA 0.9
Test and debug KBD on fpga big_core build & env FPGA
#627 opened Apr 27, 2024 by roman012285 MAFIA 0.9
@roman012285
Add the VGA CounterX CounterY to the CR space so its accessible from timing RTL design
#600 opened Mar 25, 2024 by amichai-bd MAFIA 0.7
@NoamRahat @jacobavitan837
1
update the letters font Learning Learning
#592 opened Mar 20, 2024 by jacobavitan837 MAFIA 0.7
@jacobavitan837
Refactor the D_Cache TB verification and design verificaiton
#582 opened Mar 18, 2024 by amichai-bd MAFIA 0.5
@roman012285 @amichai-bd
Automate regression analysis and have it as artifacts in the PR to main build & env
#581 opened Mar 18, 2024 by amichai-bd MAFIA 0.7
@amichai-bd
Exercise: Simple CPU Design in SystemVerilog Using MAFIA TFM build & env Learning Learning
#553 opened Mar 12, 2024 by amichai-bd
17 of 21 tasks
MAFIA 0.5
@NoamRahat @jacobavitan837
19
GCC optimization levels - See why the tests are not passing for -O1, -O3 build & env CORE_RRV documentation Improvements or additions to documentation Learning Learning
#491 opened Feb 19, 2024 by amichai-bd MAFIA 0.5
@amichai-bd
11
Create a fabric reference model for fabric verification FABRIC verificaiton
#454 opened Jan 22, 2024 by amichai-bd MAFIA 0.5
@amichai-bd
Fix the reference model to have the exact same performance as the core_rrv RTL design RV32I_REF verificaiton
#444 opened Jan 16, 2024 by amichai-bd MAFIA 0.5
@amichai-bd
Write a simple "OS-like" to wrap the program and handle the exceptions build & env documentation Improvements or additions to documentation
#436 opened Jan 15, 2024 by roman012285 MAFIA 0.9
@roman012285
Fabric - support a fabric configuration of 4 mini_cores tiles, 1 core_rrv tile, 1 uart tile FABRIC RTL design
#435 opened Jan 14, 2024 by amichai-bd MAFIA 0.9
@roman012285
core_rrv - add FPGA Support for the dram as the Far memory (128 bit accessible) CORE_RRV FPGA RTL design
#434 opened Jan 14, 2024 by amichai-bd MAFIA 0.9
@roman012285
1
Core_rrv - use the data cache for the d_mem CORE_RRV RTL design
#433 opened Jan 14, 2024 by amichai-bd MAFIA 0.9
@roman012285
fabric - Create a dedicated uart_tile FABRIC RTL design
#431 opened Jan 14, 2024 by amichai-bd MAFIA 0.9
@roman012285
MEM_SS, CACHE - add the support of mc back pressure to cache bug Something isn't working RTL design verificaiton
#330 opened Jun 29, 2023 by amichai-bd MAFIA 0.5
@amichai-bd
Cache - add performance optimization on rd exact hit MB (same word) RTL design
#233 opened Apr 27, 2023 by amichai-bd MAFIA 0.7
@amichai-bd
Uart - creat GUI to interact with the uart build & env
#207 opened Apr 1, 2023 by amichai-bd MAFIA 0.9
@roman012285
1
ProTip! Updated in the last three days: updated:>2025-02-11.