ICACHE module #768
ICACHE module #768
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| hit_index_q0 = i; | ||
| end | ||
| else begin | ||
| hit_array_q0[i] = 0; |
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Let's review this together and potentially improve the coding style
| ( | ||
| input logic clk, | ||
| input logic rst, | ||
| input logic [31:0] pcQ100H, |
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Let's add a valid bit.
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a valid bit is located inside structs towards the core and towards the i_mem
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I know it's part of the struct.. I think we should have and independent valid bit instead of the valid in the structs..
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| `MAFIA_RST_DFF(prev_hit_index_q0, hit_index_q0, clk, rst) | ||
| assign new_hit_index_q0 = ((prev_hit_index_q0 != hit_index_q0)); | ||
| assign cache_full = (tag_valid_arr == 16'hffff); |
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We should be able to parametrize the cache size
| module i_mem #(parameter DATA_WIDTH = 128, parameter ADRS_WIDTH = 32) | ||
| ( | ||
| input logic clock , | ||
| input logic [ADRS_WIDTH-1:0] address , // TODO - possible to reduce size because we use only 28 bits pc[31:4] |
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We should reduce to 28 bits.
| ( | ||
| input logic clk, | ||
| input logic rst, | ||
| input logic [31:0] pcQ100H, |
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I know it's part of the struct.. I think we should have and independent valid bit instead of the valid in the structs..
In that PR, I designed a fully associative cache with 16 cache lines (CLs) and implemented a PLRU (Pseudo-Least Recently Used) replacement mechanism. To improve the design's throughput, I aimed to minimize the number of states in the state machine.
The
i_cache_top.svfile contains two modules: one for the cache and the other for the PLRU tree algorithm. The testbench,i_cache_top_tb.sv, contains the test, which is relatively long. I verified the functionality using waveforms.I haven’t connected the
i_mem.svitself to the cache yet, but I tested it, and it’s working. I have also created a forced delay of 8 cycles.