refactor mini core load hazard detection

.github/workflows/mafia_level0.yml

@@ -48,3 +48,6 @@ jobs:
 
       - name: FABRIC 
         run:  python build.py -dut fabric -test fabric_alive -hw -sim 
+
+      - name: FABRIC 3x3 big_cores tiles 
+        run:  python build.py -dut fabric -test non_local_wr -app -sim -hw  -top fabric_big_cores_tb

FPGA/big_core_kbd_test/big_core_kbd_test.qsf

@@ -133,5 +133,5 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=sld_reserved_big_core_kbd_test_auto_signaltap_0_1_2b04," -section_id auto_signaltap_0
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp

FPGA/big_core_kbd_test/big_core_kbd_test.sv

@@ -18,14 +18,13 @@ module big_core_kbd_test(
     assign KbdDataOut  = (Rst) ? KbdDataIn  : 1'b0;
 
 // we use pll to create slower clock to capture keyboard signals in signal tapping
- pll	pll_inst (
+pll	pll_inst (
 	.areset (),
-	.inclk0 (MAX10_CLK1_50),
-	.c0 (Clock25Khz),
+	.inclk0 ( MAX10_CLK1_50 ),
+	.c0 ( Clock25Khz ),
 	.locked ()
 	);
 
 
-
 endmodule
 

FPGA/big_core_kbd_test/pll.bsf

@@ -0,0 +1,84 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 272 152)
+	(text "pll" (rect 130 0 145 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 136 25 148)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 48 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 48 80))
+	)
+	(port
+		(pt 272 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 256 50 266 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 80)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 237 66 266 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "MAX 10" (rect 234 136 497 283)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 58 59 239 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 58 72 215 155)(font "Arial" ))
+		(text "Clk " (rect 59 93 132 197)(font "Arial" ))
+		(text "Ratio" (rect 88 93 196 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 122 93 273 197)(font "Arial" ))
+		(text "DC (%)" (rect 156 93 342 197)(font "Arial" ))
+		(text "c0" (rect 62 107 132 225)(font "Arial" ))
+		(text "21/50000" (rect 80 107 196 225)(font "Arial" ))
+		(text "0.00" (rect 128 107 272 225)(font "Arial" ))
+		(text "50.00" (rect 160 107 341 225)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0))
+		(line (pt 273 0)(pt 273 153))
+		(line (pt 0 153)(pt 273 153))
+		(line (pt 0 0)(pt 0 153))
+		(line (pt 56 91)(pt 188 91))
+		(line (pt 56 104)(pt 188 104))
+		(line (pt 56 118)(pt 188 118))
+		(line (pt 56 91)(pt 56 118))
+		(line (pt 77 91)(pt 77 118)(line_width 3))
+		(line (pt 119 91)(pt 119 118)(line_width 3))
+		(line (pt 153 91)(pt 153 118)(line_width 3))
+		(line (pt 187 91)(pt 187 118))
+		(line (pt 48 48)(pt 223 48))
+		(line (pt 223 48)(pt 223 135))
+		(line (pt 48 135)(pt 223 135))
+		(line (pt 48 48)(pt 48 135))
+		(line (pt 271 64)(pt 223 64))
+		(line (pt 271 80)(pt 223 80))
+	)
+)

FPGA/big_core_kbd_test/pll.cmp

@@ -0,0 +1,25 @@
+--Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and any partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details, at
+--https://fpgasoftware.intel.com/eula.
+
+
+component pll
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

FPGA/big_core_kbd_test/pll.inc

@@ -0,0 +1,26 @@
+--Copyright (C) 2020  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and any partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details, at
+--https://fpgasoftware.intel.com/eula.
+
+
+FUNCTION pll 
+(
+	areset,
+	inclk0
+)
+
+RETURNS (
+	c0,
+	locked
+);

FPGA/big_core_kbd_test/pll.qip

@@ -2,6 +2,9 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

FPGA/big_core_kbd_test/pll.v

@@ -104,9 +104,9 @@ module pll (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 1250,
+		altpll_component.clk0_divide_by = 50000,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_multiply_by = 21,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 20000,
@@ -183,7 +183,7 @@ endmodule
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.040000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.021000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -208,9 +208,9 @@ endmodule
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25000.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.02100000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
@@ -251,9 +251,9 @@ endmodule
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1250"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "21"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
@@ -316,9 +316,9 @@ endmodule
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
 // Retrieval info: LIB_FILE: altera_mf

FPGA/big_core_kbd_test/pll_bb.v

@@ -73,7 +73,7 @@ endmodule
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.040000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.021000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -98,9 +98,9 @@ endmodule
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25000.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.02100000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
@@ -141,9 +141,9 @@ endmodule
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1250"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "21"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
@@ -206,9 +206,9 @@ endmodule
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
 // Retrieval info: LIB_FILE: altera_mf