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add crt0 and cfg file for interrupts #408

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merged 3 commits into from
Jan 4, 2024
Merged

add crt0 and cfg file for interrupts #408

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4ec9736
add files for interrupts handell
roman012285 Jan 4, 2024
aa49cab
fix interrupt issues
roman012285 Jan 4, 2024
75a1875
Merge branch 'main' of https://github.com/FPGA-MAFIA/fpga_mafia into …
roman012285 Jan 4, 2024
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9 changes: 9 additions & 0 deletions app/cfg/core_rrv_interrupts.json
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@@ -0,0 +1,9 @@
{
"I_MEM_OFFSET": 0,
"I_MEM_LENGTH": 65536,
"D_MEM_OFFSET": 65536,
"D_MEM_LENGTH": 61440,
"crt0_file" : "crt0_interrupts.S",
"rv32_gcc" : "rv32i",
"name" : "rv32i"
}
132 changes: 132 additions & 0 deletions app/crt0/crt0_interrupts.s
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@@ -0,0 +1,132 @@
_start:
.global _start
.org 0x00
nop
nop
nop
nop
nop
reset_handler:
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initialization */
la x2, _stack_start

jal x1, main //jump to main
nop
ebreak //end
nop
nop
.section .text



##################################################
# Interrupt handler for the counter in location
##################################################
handle_interrupt:
.org 0x100
# Save registers on the stack
addi sp, sp, -128 # Allocate stack space for 31 registers
sw ra, 124(sp)
sw sp, 120(sp)
sw gp, 116(sp)
sw tp, 112(sp)
sw t0, 108(sp)
sw t1, 104(sp)
sw t2, 100(sp)
sw s0, 96(sp)
sw s1, 92(sp)
sw a0, 88(sp)
sw a1, 84(sp)
sw a2, 80(sp)
sw a3, 76(sp)
sw a4, 72(sp)
sw a5, 68(sp)
sw a6, 64(sp)
sw a7, 60(sp)
sw s2, 56(sp)
sw s3, 52(sp)
sw s4, 48(sp)
sw s5, 44(sp)
sw s6, 40(sp)
sw s7, 36(sp)
sw s8, 32(sp)
sw s9, 28(sp)
sw s10, 24(sp)
sw s11, 20(sp)
sw t3, 16(sp)
sw t4, 12(sp)
sw t5, 8(sp)
sw t6, 4(sp)

handle_exception:
# General instructions for debugging
addi t0, zero, 0
addi t1, zero, 0
addi t2, zero, 0

restore_and_return:
# Restore registers from the stack
lw ra, 124(sp)
lw sp, 120(sp)
lw gp, 116(sp)
lw tp, 112(sp)
lw t0, 108(sp)
lw t1, 104(sp)
lw t2, 100(sp)
lw s0, 96(sp)
lw s1, 92(sp)
lw a0, 88(sp)
lw a1, 84(sp)
lw a2, 80(sp)
lw a3, 76(sp)
lw a4, 72(sp)
lw a5, 68(sp)
lw a6, 64(sp)
lw a7, 60(sp)
lw s2, 56(sp)
lw s3, 52(sp)
lw s4, 48(sp)
lw s5, 44(sp)
lw s6, 40(sp)
lw s7, 36(sp)
lw s8, 32(sp)
lw s9, 28(sp)
lw s10, 24(sp)
lw s11, 20(sp)
lw t3, 16(sp)
lw t4, 12(sp)
lw t5, 8(sp)
lw t6, 4(sp)
addi sp, sp, 128 # Deallocate stack space
mret # Return from interrupt
69 changes: 36 additions & 33 deletions source/core_rrv/core_rrv.sv
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Expand Up @@ -57,21 +57,22 @@ logic [31:0] CsrReadDataQ102H; // data red from CSR
logic [31:0] CsrWriteDataQ102H; // data writen to csr

// Control bits
logic BranchCondMetQ102H;
logic ReadyQ100H;
logic ReadyQ102H;
logic ReadyQ103H;
logic ReadyQ104H;
logic ReadyQ105H;
t_csr_hw_updt CsrHwUpdtQ102H;
t_core_rrv_ctrl Ctrl;
t_ctrl_if CtrlIf;
t_ctrl_rf CtrlRf;
t_ctrl_exe CtrlExe;
t_ctrl_mem1 CtrlMem1;
t_ctrl_wb CtrlWb;
t_csr_inst_rrv CtrlCsr;
t_csr_pc_update CsrPcUpdateQ102H;
logic BranchCondMetQ102H;
logic ReadyQ100H;
logic ReadyQ102H;
logic ReadyQ103H;
logic ReadyQ104H;
logic ReadyQ105H;
logic ValidInstQ105H;
t_csr_interrupt_update CsrInterruptUpdateQ102H;
t_core_rrv_ctrl Ctrl;
t_ctrl_if CtrlIf;
t_ctrl_rf CtrlRf;
t_ctrl_exe CtrlExe;
t_ctrl_mem1 CtrlMem1;
t_ctrl_wb CtrlWb;
t_csr_inst_rrv CtrlCsr;
t_csr_pc_update CsrPcUpdateQ102H;

//////////////////////////////////////////////////////////////////////////////////////////////////
// _____ __ __ _____ _ ______ ____ __ ___ ___ _ _
Expand Down Expand Up @@ -135,15 +136,16 @@ core_rrv_ctrl core_rrv_ctrl (
.ReadyQ104H (ReadyQ104H), // output
.ReadyQ105H (ReadyQ105H), // output
// output ctrl signals
.CtrlIf (CtrlIf ), //output
.CtrlRf (CtrlRf ), //output
.CtrlExe (CtrlExe ), //output
.CtrlCsr (CtrlCsr ), //output
.CtrlMem1 (CtrlMem1 ), //output
.CtrlWb (CtrlWb ), //output
.CtrlIf (CtrlIf ), //output
.CtrlRf (CtrlRf ), //output
.CtrlExe (CtrlExe ), //output
.CtrlCsr (CtrlCsr ), //output
.CtrlMem1 (CtrlMem1 ), //output
.CtrlWb (CtrlWb ), //output
// output data path signals
.ImmediateQ101H (ImmediateQ101H ), //output
.CsrHwUpdtQ102H (CsrHwUpdtQ102H ) //output
.ImmediateQ101H (ImmediateQ101H ), //output
.CsrInterruptUpdateQ102H (CsrInterruptUpdateQ102H ), //output
.ValidInstQ105H (ValidInstQ105H )
);

core_rrv_rf
Expand All @@ -161,7 +163,7 @@ core_rrv_rf (
.PcQ102H (PcQ102H), // output
.ImmediateQ102H (ImmediateQ102H), // output
.RegRdData1Q102H (RegRdData1Q102H), // output
.RegRdData2Q102H (RegRdData2Q102H) // output
.RegRdData2Q102H (RegRdData2Q102H) // output
);

//////////////////////////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -210,17 +212,18 @@ core_rrv_exe core_rrv_exe (
);

core_rrv_csr core_rrv_csr (
.Clk (Clock ),
.Rst (Rst ),
.PcQ102H (PcQ102H ),
.Clk (Clock ),
.Rst (Rst ),
.PcQ102H (PcQ102H ),
// Inputs from the core
.CsrInstQ102H (CtrlCsr ),
.CsrWriteDataQ102H (CsrWriteDataQ102H ),
.CsrHwUpdtQ102H (CsrHwUpdtQ102H ), // FIXME: support hardware update for CSR (example: mstatus, mcause, ...)
.CsrPcUpdateQ102H (CsrPcUpdateQ102H ),
.interrupt_counter_expired ( ),
.CsrInstQ102H (CtrlCsr ),
.CsrWriteDataQ102H (CsrWriteDataQ102H ),
.ValidInstQ105H (ValidInstQ105H ),
.CsrInterruptUpdateQ102H (CsrInterruptUpdateQ102H), // FIXME: support hardware update for CSR (example: mstatus, mcause, ...)
.CsrPcUpdateQ102H (CsrPcUpdateQ102H ),
.interrupt_counter_expired ( ),
// Outputs to the core
.CsrReadDataQ102H (CsrReadDataQ102H )
.CsrReadDataQ102H (CsrReadDataQ102H )
);


Expand Down
55 changes: 27 additions & 28 deletions source/core_rrv/core_rrv_csr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -2,17 +2,18 @@
module core_rrv_csr
import core_rrv_pkg::*;
(
input logic Clk,
input logic Rst,
input logic [31:0] PcQ102H,
input logic Clk,
input logic Rst,
input logic [31:0] PcQ102H,
// Inputs from the core
input var t_csr_inst_rrv CsrInstQ102H,
input logic [31:0] CsrWriteDataQ102H,
input var t_csr_hw_updt CsrHwUpdtQ102H, // 32-bit data to be written into the CSR
input var t_csr_inst_rrv CsrInstQ102H,
input logic [31:0] CsrWriteDataQ102H,
input var t_csr_interrupt_update CsrInterruptUpdateQ102H, // 32-bit data to be written into the CSR
input ValidInstQ105H,
// Outputs to the core
output var t_csr_pc_update CsrPcUpdateQ102H,
output logic interrupt_counter_expired,
output logic [31:0] CsrReadDataQ102H // 32-bit data read from the CSR
output var t_csr_pc_update CsrPcUpdateQ102H,
output logic interrupt_counter_expired,
output logic [31:0] CsrReadDataQ102H // 32-bit data read from the CSR
);

// Define the CSR registers
Expand Down Expand Up @@ -174,24 +175,20 @@ always_comb begin
// 3. illegal CSR access
// 4. breakpoint
//FIXME - please review the values of the exceptions - read the spec
if(CsrHwUpdtQ102H.illegal_instruction) begin
if(CsrInterruptUpdateQ102H.illegal_instruction) begin
next_csr.csr_mcause = 32'h00000002;
next_csr.csr_mtvec = 32'h00000100;
next_csr.csr_mepc = PcQ102H;
end
if(CsrHwUpdtQ102H.misaligned_access) begin
if(CsrInterruptUpdateQ102H.misaligned_access) begin
next_csr.csr_mcause = 32'h00000004;
next_csr.csr_mtvec = 32'h00000200; // TODO - possible changing of the address
next_csr.csr_mepc = PcQ102H;
end
if(CsrHwUpdtQ102H.illegal_csr_access) begin
if(CsrInterruptUpdateQ102H.illegal_csr_access) begin
next_csr.csr_mcause = 32'h0000000B;
next_csr.csr_mtvec = 32'h00000300; // TODO - possible changing of the address
next_csr.csr_mepc = PcQ102H;
end
if(CsrHwUpdtQ102H.breakpoint) begin
if(CsrInterruptUpdateQ102H.breakpoint) begin
next_csr.csr_mcause = 32'h00000003;
next_csr.csr_mtvec = 32'h00000400; // TODO - possible changing of the address
next_csr.csr_mepc = PcQ102H;
end
// handle HW interrupts:
Expand All @@ -201,15 +198,15 @@ always_comb begin
//if(interrupt_counter_expired) begin
// next_csr.csr_mepc = PcQ102H;
//end
//if(CsrHwUpdtQ102H.external_interrupt) next_csr.csr_mcause = 32'h0000000B;
//if(CsrInterruptUpdateQ102H.external_interrupt) next_csr.csr_mcause = 32'h0000000B;

//==========================================================================
// ---- RO/V CSR - writes from RTL ----
//==========================================================================
{csr_cycle_low_overflow , next_csr.csr_cycle_low} = csr.csr_cycle_low + 1'b1;
next_csr.csr_cycle_high = csr.csr_cycle_high + csr_cycle_low_overflow;
csr_cycle_high_low = {csr.csr_cycle_high, csr.csr_cycle_low};
if(CsrHwUpdtQ102H.ValidInstQ105H) begin
if(ValidInstQ105H) begin
{csr_instret_low_overflow , next_csr.csr_instret_low} = csr.csr_instret_low + 1'b1;
next_csr.csr_instret_high = csr.csr_instret_high + csr_instret_low_overflow;
csr_instret_high_low = {csr.csr_instret_high, csr.csr_instret_low};
Expand Down Expand Up @@ -292,17 +289,19 @@ end

// Update program counter
logic BeginInterrupt;
assign BeginInterrupt = (CsrHwUpdtQ102H.illegal_instruction) || (CsrHwUpdtQ102H.misaligned_access) || (CsrHwUpdtQ102H.illegal_csr_access) || (CsrHwUpdtQ102H.breakpoint) || (CsrHwUpdtQ102H.external_interrupt) || (CsrHwUpdtQ102H.timer_interrupt);
assign BeginInterrupt = (CsrInterruptUpdateQ102H.illegal_instruction || CsrInterruptUpdateQ102H.misaligned_access
|| CsrInterruptUpdateQ102H.illegal_csr_access || CsrInterruptUpdateQ102H.breakpoint
|| CsrInterruptUpdateQ102H.external_interrupt || CsrInterruptUpdateQ102H.timer_interrupt);

//assign CsrPcUpdateQ102H.InterruptJumpEnQ102H = BeginInterrupt;
//assign CsrPcUpdateQ102H.InterruptJumpAddressQ102H = next_csr.csr_mtvec;
//assign CsrPcUpdateQ102H.InteruptReturnEnQ102H = CsrHwUpdtQ102H.Mret;
//assign CsrPcUpdateQ102H.InteruptReturnAddressQ102H = next_csr.csr_mepc;
assign CsrPcUpdateQ102H.InterruptJumpEnQ102H = BeginInterrupt;
assign CsrPcUpdateQ102H.InterruptJumpAddressQ102H = next_csr.csr_mtvec;
assign CsrPcUpdateQ102H.InteruptReturnEnQ102H = CsrInterruptUpdateQ102H.Mret;
assign CsrPcUpdateQ102H.InteruptReturnAddressQ102H = next_csr.csr_mepc;

assign CsrPcUpdateQ102H.InterruptJumpEnQ102H = 0;
assign CsrPcUpdateQ102H.InterruptJumpAddressQ102H = 0;
assign CsrPcUpdateQ102H.InteruptReturnEnQ102H = 0;
assign CsrPcUpdateQ102H.InteruptReturnAddressQ102H = 0;
//assign CsrPcUpdateQ102H.InterruptJumpEnQ102H = 0;
//assign CsrPcUpdateQ102H.InterruptJumpAddressQ102H = 0;
//assign CsrPcUpdateQ102H.InteruptReturnEnQ102H = 0;
//assign CsrPcUpdateQ102H.InteruptReturnAddressQ102H = 0;

//assign MePc = csr.csr_mepc;
// assign csr.csr_mvendorid = 32'b0; // CSR_MVENDORID
Expand Down
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