adding state machine to prefetcher + test bench + adjusting interface…

…s in IFU top

source/ifu/ifu.sv

@@ -28,6 +28,7 @@ import ifu_pkg::*;
 // data insertion
 logic insertionOnMiss;
 logic insertionOnPrefetch;
+logic p_reqSent;
 
 // cache signals
 logic [TAG_WIDTH - 1: 0] c_mem_reqTagOut;
@@ -37,12 +38,27 @@ logic c_mem_reqTagValidOut;
 logic [TAG_WIDTH - 1: 0] p_mem_reqTagOut;
 logic p_mem_reqTagValidOut;
 
+// cache <-> prefetcher 
+logic                    c2p_rspTagValid; 
+logic                    c2p_rspTagStatus;
+logic [TAG_WIDTH - 1: 0] c2p_rspTag;
+logic                    p2c_reqTagValid;
+logic [TAG_WIDTH - 1: 0] p2c_reqTag;
+
 ///////////
 // Cache //
 ///////////
 ifu_cache ifu_cache (
     .Clock(Clock),                                          // Input
     .Rst(Rst),                                              // Input
+
+    // Prefetcher Interface
+    .pref_reqTagValidIn(p2c_reqTag),                        // Input
+    .pref_reqTagIn(p2c_reqTagValid),                        // Input
+    .pref_rspTagValidOut(c2p_rspTagValid),                  // Output
+    .pref_rspTagStatusOut(c2p_rspTagStatus),                // Output
+    .pref_rspTagOut(p2c_reqTag),                            // Output
+
     // CPU Interface
     .cpu_reqAddrIn(cpu_reqAddrIn),                          // Input
     .cpu_rspAddrOut(cpu_rspAddrOut),                        // Output
@@ -63,6 +79,17 @@ ifu_cache ifu_cache (
 ifu_prefetcher ifu_prefetcher (
     .Clock(Clock),                                          // Input
     .Rst(Rst),                                              // Input
+
+    // Cache Interface
+    .cache_rspTagValidIn(c2p_rspTagValid),                  // input
+    .cache_rspTagStatusIn(c2p_rspTagStatus),                // input
+    .cache_rspTagIn(c2p_rspTag),                            // input
+    .cache_reqTagValidOut(p2c_reqTagValid),                 // Output 
+    .cache_reqTagOut(p2c_reqTag),                           // Output 
+
+    // IFU signals
+    .ifu_prefReqSent(p_reqSent),                            // Input
+
     // CPU Interface
     .cpu_reqAddrIn(cpu_reqAddrIn),                          // Input
 
@@ -87,17 +114,24 @@ assign insertionOnPrefetch = (mem_rspInsLineValidIn == VALID) && (p_mem_reqTagVa
 always_comb begin
 
     if (insertionOnMiss) begin
-       mem_reqTagOut = c_mem_reqTagOut;
-       mem_reqTagValidOut = VALID;
+        mem_reqTagOut = c_mem_reqTagOut;
     end 
 
     if (insertionOnPrefetch) begin
         mem_reqTagOut = p_mem_reqTagOut;
+        p_reqSent = VALID;
+    end
+
+    if (insertionOnMiss || insertionOnPrefetch) begin
         mem_reqTagValidOut = VALID;
     end
 
 end
 
+///////////////////////////
+// Always_FF Statement //
+///////////////////////////
+
 
 endmodule
 

source/ifu/ifu_cache.sv

@@ -7,6 +7,13 @@ import ifu_pkg::*;
     input logic Clock,
     input logic Rst,
 
+    // Prefetcher Interface
+    input logic pref_reqTagValidIn,
+    input logic [TAG_WIDTH - 1 : 0] pref_reqTagIn,
+    output logic pref_rspTagValidOut,
+    output logic cache_rspTagStatusOut,
+    output logic [TAG_WIDTH - 1 : 0] pref_rspTagOut,
+
     // CPU Interface
     input logic [ADDR_WIDTH-1:0] cpu_reqAddrIn, // requested addr by cpu
     output logic [ADDR_WIDTH-1:0] cpu_rspAddrOut, // address of the line in the response to cpu
@@ -42,9 +49,11 @@ data_arr_t dataArray [NUM_LINES];
 logic [P_BITS - 1:0] replacementLine;
 
 // Hit 
-logic [P_BITS - 1:0] hitPosition;
-logic [NUM_TAGS - 1:0] hitArray;
-logic hitStatus;
+logic [P_BITS - 1:0] cpu_hitPosition;
+logic [NUM_TAGS - 1:0] cpu_hitArray;
+logic [NUM_TAGS - 1:0] pref_hitArray;
+logic cpu_hitStatus;
+logic pref_hitStatus;
 
 
 // PLRU
@@ -62,16 +71,17 @@ logic [P_BITS - 1:0] plruAccessLine;
 assign cpu_reqTagIn = cpu_reqAddrIn[ADDR_WIDTH - 1:OFFSET_WIDTH];
 
 // Hit
-assign hitStatus = |hitArray;
-assign mem_reqTagValidOut = !hitStatus;
+assign cpu_hitStatus = |cpu_hitArray;
+assign pref_hitStatus = |pref_hitArray;
+assign mem_reqTagValidOut = !cpu_hitStatus;
 
 // Insertion
 assign dataInsertion = mem_rspInsLineValidIn && mem_reqTagValidOut;
 
 // Debug
-assign hitStatusOut = hitStatus;
+assign hitStatusOut = cpu_hitStatus;
 assign debug_plruTree = plruTree;
-assign debug_plruIndex = replacementLine;
+
 
 // Flattened debug arrays for monitoring
 generate
@@ -93,23 +103,24 @@ always_comb begin
     plruAccessLineValid = 0;
     replacementLine = 0;
     updatedPlruTree = plruTree;
+    pref_rspTagValidOut = !VALID;
 
     // Hit Status
     for (int i = 0; i < NUM_TAGS; i++) begin
         if (cpu_reqTagIn == tagArray[i].tag && tagArray[i].valid == VALID) begin
-            hitArray[i] = 1;
-            hitPosition = i;
+            cpu_hitArray[i] = 1;
+            cpu_hitPosition = i;
         end else begin
-            hitArray[i] = 0;
+            cpu_hitArray[i] = 0;
         end
     end
 
     // Cache Action
-    if (hitStatus == HIT) begin
+    if (cpu_hitStatus == HIT) begin
         cpu_rspAddrOut = cpu_reqAddrIn;
-        cpu_rspInsLineOut = dataArray[hitPosition];
+        cpu_rspInsLineOut = dataArray[cpu_hitPosition];
         cpu_rspInsLineValidOut = VALID;
-        plruAccessLine = hitPosition; 
+        plruAccessLine = cpu_hitPosition; 
         plruAccessLineValid = VALID;
     end else begin
         cpu_rspInsLineValidOut = !VALID;
@@ -155,6 +166,23 @@ always_comb begin
         end
     end 
 
+    // prefetcher check
+    for (int i = 0; i < NUM_TAGS; i++) begin
+        if (pref_reqTagIn == tagArray[i].tag && tagArray[i].valid == VALID) begin
+            pref_hitArray[i] = 1;
+        end else begin
+            pref_hitArray[i] = 0;
+        end
+    end
+
+    if (pref_reqTagValidIn) begin
+        cache_rspTagStatusOut = pref_hitStatus;
+        pref_rspTagValidOut = VALID;
+        pref_rspTagOut = pref_reqTagIn;
+    end else begin
+        cache_rspTagStatusOut = !VALID;
+    end
+
 end
 
 ///////////////////////////
@@ -168,7 +196,7 @@ always_ff @(posedge Clock or posedge Rst) begin
         end
         plruTree <= 15'b0;
     end else begin
-        if (hitStatus == HIT) begin
+        if (cpu_hitStatus == HIT) begin
             plruTree <= updatedPlruTree; 
         end
 
@@ -177,6 +205,7 @@ always_ff @(posedge Clock or posedge Rst) begin
             tagArray[replacementLine].valid <= VALID;
             tagArray[replacementLine].tag[TAG_WIDTH-1:0] <= mem_rspTagIn[TAG_WIDTH-1:0];
             plruTree <= updatedPlruTree; 
+            debug_plruIndex <= replacementLine;
         end
     end
 end

source/ifu/ifu_prefetcher.sv

@@ -3,54 +3,146 @@
 module ifu_prefetcher
 import ifu_pkg::*;
 (
+
+    // debug 
+    output [1:0] current_stateOut,
+
     // Chip Signals
     input logic Clock,
     input logic Rst,
 
+    // Cache Interface
+    input logic cache_rspTagValidIn, 
+    input logic cache_rspTagStatusIn, 
+    input logic [TAG_WIDTH - 1 : 0] cache_rspTagIn,
+    output logic cache_reqTagValidOut, // 
+    output logic [TAG_WIDTH - 1 : 0] cache_reqTagOut, // check if cache has the line we want to get 
+
+    // IFU signals
+    input logic ifu_prefReqSent,
+
     // CPU Interface
     input logic [ADDR_WIDTH-1:0] cpu_reqAddrIn, // requested addr by cpu
-
-    input logic [TAG_WIDTH-1:0] mem_rspTagIn, // tag of the line provided by response of the memory
-    input logic mem_rspInsLineValidIn, // the line is ready in the response and can be read by the cache
 
     // Memory Interface
+    input logic [TAG_WIDTH-1:0] mem_rspTagIn, // tag of the line provided by response of the memory
+    input logic mem_rspInsLineValidIn, // the line is ready in the response and can be read by the cache
     output logic [TAG_WIDTH - 1:0] mem_reqTagOut, // Predicted address sent to memory
     output logic mem_reqTagValidOut             // Indicates if the prefetch request is valid
+
 );
 
+
+///////////////////
+// State Encoding //
+///////////////////
+typedef enum logic [1:0] { 
+    s_check = 2'b00,
+    s_request = 2'b01,
+    s_sleep = 2'b10,
+    s_count = 2'b11
+} pref_state_t;
+
+
+
 
 ///////////////////
 // Logic Defines //
 ///////////////////
+
+// state machine
+pref_state_t current_state, next_state;
+
 logic [TAG_WIDTH - 1 : 0] cpu_reqTagIn;
-logic mem_reqLineReady;
+logic [TAG_WIDTH - 1 : 0] cpu_reqTagIn_buffer;
+logic sleep;
+logic [1:0] cycleCounter; 
 
 /////////////
 // Assigns //
 /////////////
+assign current_stateOut = current_state;
 assign cpu_reqTagIn = cpu_reqAddrIn[ADDR_WIDTH - 1 : OFFSET_WIDTH];
 assign mem_reqTagOut = cpu_reqTagIn + 1;
-assign mem_reqLineReady = mem_rspTagIn == mem_reqTagOut  &&  mem_rspInsLineValidIn;
+assign cache_reqTagOut = cpu_reqTagIn + 1;
+assign sleep = (((cache_rspTagIn == cache_reqTagOut) && cache_rspTagValidIn && cache_rspTagStatusIn) || // if cache has the next line sleep
+               ((mem_rspTagIn == mem_reqTagOut)  &&  mem_rspInsLineValidIn) || // if line is brought from memory sleep
+                ifu_prefReqSent);                                              // if the request was already sent then we don't need to send again
+
 
 ///////////////////////////
 // Always Comb Statement //
 ///////////////////////////
 always_comb begin
+
+    case (current_state)
 
-    if (mem_reqLineReady) begin   // if the memory supplied us with the prefetched line
-        mem_reqTagValidOut = !VALID;
-    end else begin
-        mem_reqTagValidOut = VALID;
-    end
+        s_check: begin
+            cache_reqTagValidOut = VALID;
+            if ((cache_rspTagIn == cache_reqTagOut) && cache_rspTagValidIn) begin
+                cache_reqTagValidOut = !VALID;
+                if (cache_rspTagStatusIn) begin
+                    mem_reqTagValidOut = !VALID;
+                    next_state = s_sleep;
+                end else begin
+                    mem_reqTagValidOut = VALID;
+                    next_state = s_request;
+                end
+            end
+        end
+
+        s_request: begin
+            mem_reqTagValidOut = VALID;
+            if(sleep) begin
+                mem_reqTagValidOut = !VALID;
+                next_state = s_sleep;
+            end
+        end
+
+        s_sleep: begin
+            mem_reqTagValidOut = !VALID;
+            cache_reqTagValidOut = !VALID;
+            if ((cpu_reqTagIn_buffer != cpu_reqTagIn) || (cycleCounter == 2'b11)) begin // if PC-Tag changes or 4 cycles have passed since last request
+                next_state = s_check;
+            end
+        end
+
+        default: begin
+            next_state = s_check;
+            mem_reqTagValidOut = !VALID;
+            cache_reqTagValidOut = !VALID;
+        end
+
+    endcase
 
 end
 
 
 ///////////////////////////
 // Always_ff Statement ////
 ///////////////////////////
+always_ff @(posedge Clock or posedge Rst) begin
+
+    cpu_reqTagIn_buffer <= cpu_reqTagIn;
+
+    if (Rst) begin
+        cycleCounter <= 2'b0;
+        current_state <= s_check;
+    end else begin
+
+        current_state <= next_state;
+
+        if (next_state == s_sleep) begin
+            cycleCounter <= 2'b0;
+        end else begin 
+            cycleCounter <= cycleCounter + 1;
+        end
 
 
+    end
+
+end
+
 endmodule
 
 

verif/ifu/file_list/ifu_verif_list.f

@@ -1,3 +1,4 @@
 +incdir+../../../source/common/
 +incdir+../../../verif/ifu/tb/
 ../../../verif/ifu/tb/ifu_cache_tb.sv
+../../../verif/ifu/tb/ifu_prefetcher_tb.sv