This repository contains the code and documentation for a digital system design project implemented using MATLAB and Verilog. The project focuses on designing and implementing a FIR (Finite Impulse Response) Low Pass Filter (LPF) within the context of a Digital Signal Synthesizer (DDS).
Figure 1: Direct Digital Synthesizer Architecture Proposal
Figure 2: Direct Digital Synthesizer Architecture realization in Verilog
The project involves the following components:
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System Architecture: The architecture of the digital system, including the data path, control path, and top-level system design.
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Filter Design in MATLAB: Designing a FIR LPF using MATLAB's Filter Designer tool, specifying frequency requirements and obtaining filter coefficients.
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Filter Implementation in Verilog: Implementing the FIR LPF in Verilog, integrating it into the larger DDS system architecture.
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Verification and Simulation: Validating the Verilog implementation through simulation and comparing results with MATLAB's ideal plots.
To reproduce the results or run simulations:
- Navigate to the relevantS Source code repositories to get the source codes..
- You can follow the instructions in the provided documents/reports in this repository, which gives an overview of each step taking in this project.
- Execute the scripts or commands as instructed to run simulations, generate plots, or analyze results.
This project is licensed under the GNU License.