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@AUCOHL

AUC Open Source Hardware Lab

Projects by the Open Source Hardware Lab at the American University in Cairo (AUC).

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  1. Fault Public

    A complete open-source design-for-testing (DFT) Solution

    Swift 148 32

  2. DFFRAM Public

    Standard Cell Library based Memory Compiler using FF/Latch cells

    Verilog 144 33

Repositories

Showing 10 of 27 repositories
  • Lighter Public

    An automatic clock gating utility

    Verilog 47 Apache-2.0 5 3 0 Updated Apr 15, 2025
  • OpenLane Public Forked from efabless/openlane2

    Premier open-source RTL-to-GDSII flow

    Python 2 Apache-2.0 59 0 0 Updated Apr 14, 2025
  • openlane-step-unit-tests Public Forked from efabless/openlane2-step-unit-tests

    Step-specific Unit Tests for OpenLane

    Verilog 0 Apache-2.0 4 0 0 Updated Feb 26, 2025
  • frigate-os Public Forked from efabless/frigate-os
    Verilog 0 Apache-2.0 10 0 0 Updated Feb 26, 2025
  • openlane-ci-designs Public Forked from efabless/openlane2-ci-designs

    Continuous Integration Designs for OpenLane 2.0.0 or higher

    Verilog 0 7 0 0 Updated Feb 23, 2025
  • Fault Public

    A complete open-source design-for-testing (DFT) Solution

    Swift 148 Apache-2.0 32 9 (1 issue needs help) 0 Updated Nov 2, 2024
  • DFFRAM Public

    Standard Cell Library based Memory Compiler using FF/Latch cells

    Verilog 144 Apache-2.0 33 28 4 Updated Jun 15, 2024
  • RTL-Repo Public

    RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

    Python 13 Apache-2.0 1 0 0 Updated Jun 5, 2024
  • Stdcells Public

    The Standard Cell Libraries Used By The Cloud V Platform

    Verilog 1 1 0 0 Updated Mar 17, 2023
  • sky130-builds Public archive

    What it says on the tin

    Python 4 2 0 0 Updated Apr 26, 2022
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