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[Bugfix][Perf][SM70/SM75] Widen QSA sparse launch profile to pre-Ampere - #469

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Peuqui:qsa-pre-ampere-launch-profile
Sep 3, 2026
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yangzhuxinyzx merged 1 commit into
1CatAI:mainfrom
Peuqui:qsa-pre-ampere-launch-profile

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@Peuqui

@Peuqui Peuqui commented Sep 3, 2026

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Follow-up to #441, as requested there. Unlike the closed #455 (our dispatch mistake — apologies again), every number below was measured against this file (nvidia/ops/qsa.py at ca73a34) on both of our pre-Ampere cards.

What

Widen the existing SM70 branch in _qsa_sparse_launch_profile to all pre-Ampere devices and let it pick the narrow 16-column, four-warp tile:

  • callsite gate: current_platform.is_device_capability(70)not current_platform.has_device_capability(80) (SM80+ keeps the GB300 table bit-for-bit),
  • the pre-Ampere branch sets block_n = 16, partial_warps = 4 for every prefill regime (the branch only fires when the GB300 table chose block_n == 64, so the small-batch decode profiles are untouched),
  • both test files updated accordingly.

Why

  1. SM75 cannot launch the current profiles at all. At D=256 the 64-column tile exceeds Turing's 64 KiB shared-memory limit: Triton raises OutOfResources for every prefill regime (rows ≥ 64 measured). The existing SM70 retune does not apply on SM75, and even force-applied it only helps ≥ 512 programs (N32) — the 33..256-program regimes keep N64 and still fail.
  2. N16/W4 is also faster where the current profiles do run. 1.17–2.6× on V100 and 1.16–1.17× on SM75 against the best previously runnable profile, with identical outputs.

Measurements

Production Qwen4Exp TP2 geometry (12 query heads, 1 KV head, D=256, TOPK=2048, PAGE_SIZE=16, bf16 caches, 16k-token KV), medians of 30 CUDA-event-timed calls after 3 warmups. base_programs = rows (1 KV head).

Tesla V100-PCIE-32GB (SM70):

rows GB300 profile (N64/W2) current SM70 retune this PR (N16/W4)
64 13.38 ms 2.40 ms (N64/S8/W4) 1.11 ms
256 50.62 ms 9.13 ms (N64/S8/W4) 3.54 ms
512 100.69 ms 8.63 ms (N32/S4/W4) 6.96 ms
1024 262.67 ms 17.18 ms (N32/S1/W4) 14.71 ms
2048 525.24 ms 32.98 ms (N32/S1/W4) 27.39 ms

Quadro RTX 8000 (SM75):

rows current dispatch (GB300, no retune) SM70 retune force-applied this PR (N16/W4)
64 OutOfResources OutOfResources (N64/S8/W4) 2.08 ms
256 OutOfResources OutOfResources (N64/S8/W4) 6.30 ms
512 OutOfResources 14.41 ms (N32/S4/W4) 12.29 ms
1024 OutOfResources 29.27 ms (N32/S1/W4) 25.23 ms
2048 OutOfResources 56.96 ms (N32/S1/W4) 48.75 ms

Methodology: the file at ca73a34 is loaded as-is via importlib and only _qsa_sparse_launch_profile is overridden per data point, so launch, split merge and workspaces are exactly the shipped code paths. Every profile's output was cross-checked against the default profile's output — identical within bf16 split-reduction-order tolerance. With the patch applied, the default dispatch reproduces the N16 column on both cards.

Decode is deliberately untouched: at rows 1/6/8 the GB300 table already picks the narrow high-split profiles, and they win (forcing S8 at rows=1 measured 3× slower). Also untouched: sm70_single_token in qsa_mqa_paged, the TP4 group_size == 6 warp special case, and everything SM80+.

Open question

Your N32 choice at ≥ 512 programs was tuned on the exact 512/8192-row shapes; on our cards N16 measures ahead of N32 there too (SM70 1.20×, SM75 1.16–1.17×). If you prefer to keep N32 on SM70, the minimal alternative is widening only the gate — but that leaves the 33..256-program regimes unable to launch on SM75, which is why this PR proposes N16 across the pre-Ampere prefill branch. Happy to rerun any shape you care about on V100-PCIE or RTX 8000.

Duplication check, tests, and AI assistance

Per the repository's agent guidelines:

  • Duplication: gh pr list --state open --search for "qsa launch profile", "pre-ampere" and "441 in:body" each return only this PR. The related closed [Perf] Pre-Ampere tile profiles for the QSA prefill dispatch (#441) #455 was our own earlier attempt that measured the wrong file; this PR supersedes it as discussed in [Perf][SM70/SM75] Pre-Ampere tuning findings from a mixed Volta/Turing rig — QSA #441.
  • Tests: both touched test files were run in full against the patched module (Python 3.12, torch 2.10.0, Tesla V100): python -m pytest tests/models/qwen4_exp/test_qsa_launch_profile.py tests/models/qwen4_exp/test_qsa_ops.py -v18 passed (7 launch-profile cases + 11 ops tests, including every untouched one).
  • AI assistance: this change was AI-assisted (Claude, see commit trailer). The submitter reviewed every changed line, ran all measurements on his own hardware, and can defend the change end-to-end.

Refs #441.

🤖 Generated with Claude Code

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The GB300 prefill profiles select a 64-column tile that cannot launch on
SM75 at D=256 (Triton OutOfResources against Turing's 64 KiB shared
memory), and the existing SM70 retune does not apply there. Gate the
branch on compute capability < 8.0 and pick the 16-column four-warp
tile, which launches on both pre-Ampere architectures and measures
1.16-2.6x faster than the best previously runnable profile across the
64..2048-row prefill regimes (V100-PCIE-32GB, Quadro RTX 8000; 1CatAI#441).
Small-batch decode profiles and the sm80+ table are unchanged.

Co-authored-by: Claude <noreply@anthropic.com>
Signed-off-by: Peuqui <peuqui@github.com>

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Validated against main after #466: merge is conflict-free; targeted QSA suites report 20 passed, 1 skipped; targeted pre-commit passes. The change remains a pre-Ampere fallback/profile improvement and does not override the grouped Page4 fast path.

@yangzhuxinyzx
yangzhuxinyzx merged commit 65d25c1 into 1CatAI:main Sep 3, 2026
SabaTech-dev pushed a commit to SabaTech-dev/1Cat-vLLM that referenced this pull request Sep 3, 2026
…stream 1CatAI#469

Assisted-by: GLM (zai/glm-5.3-flash)
Signed-off-by: Joker <joker@sabatech.dev>
SabaTech-dev pushed a commit to SabaTech-dev/1Cat-vLLM that referenced this pull request Sep 3, 2026
Assisted-by: GLM (zai/glm-5.3-flash)
Signed-off-by: Joker <joker@sabatech.dev>
SabaTech-dev pushed a commit to SabaTech-dev/1Cat-vLLM that referenced this pull request Sep 3, 2026
…QSA tiles

Own-measurement verification of the community claim (narrow 16-col
tiles 19.3x vs GB300 profile on V100, D=256 TOPK2048 2048-token
prefill): reproduced at 18.53x on our hardware. Run per-GPU via
CUDA_VISIBLE_DEVICES.

Assisted-by: GLM (zai/glm-5.3-flash)
Signed-off-by: Joker <joker@sabatech.dev>
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2 participants