[Perf] Pre-Ampere tile profiles for the QSA prefill dispatch (#441)

[Peuqui]

Follow-up to #441 as requested — the QSA prefill retune we run in production on a mixed Volta/Turing box (2× Quadro RTX 8000 sm75, 3× Tesla V100 sm70).

What

The dispatch table in qwen4_exp/amd/ops/qsa.py ("Tuned on GB300") is used unchanged on pre-Ampere cards, where two warps cannot hide the emulated-bf16 latency. This PR adds, ahead of that table:

1. a capability branch selecting narrow 4-warp tiles (16/8/4, 16/4/4, 16/1/4 by base_programs) for compute_capability < 8 on the prefill branch (base_programs >= 32). The decode/verify branches already run the optimal narrow profiles and are untouched.
2. a shared-memory clamp that sizes the tile against the device's actual opt-in limit (2 * BLOCK_N * HEAD_DIM * itemsize + BLOCK_M * HEAD_DIM * 4) instead of assuming the GB300 budget — Turing grants 64 KiB, Volta 96 KiB.

Both are CUDA-only; ROCm keeps its measured single-stage behaviour exactly as before. Pure insertions, no existing profile changes for sm80+.

Measurements

2048-token prefill chunk, production geometry (H12/KV1/D256, TOPK 2048), harness tools/qsa_bench.py in our fork:

Card	GB300 profile	pre-Ampere profile	factor
V100 (96 KB smem)	527 ms (N64/S1/W2)	27.3 ms (N16/S1/W4)	19.3×
RTX 8000 (64 KB)	199.7 ms (clamped N32/W2)	47.9 ms (N16/S4/W4)	4.2×

End to end on Qwen3.8-Flash-Next-180B (TP2×PP2, 262k context): prefill 392–448 → 1482–1696 tok/s, cold-turn TTFT 67 → 25 s, coherence 3/3 (caveats on the absolute prefill number as discussed in #441; the ratio is the load-bearing part).

Numerics: 9.77e-04 max deviation against the production path, while the kernel already scatters 4.88e-04 against itself across split reduction orders — one to two ULP in bf16. An A/B with identical prompts showed no quality difference.

Notes

• Per qwen4_exp/__init__.py, pre-Ampere takes the amd/ branch, so only that file is touched; the nvidia/ twin is dead code on these cards.
• Happy to extend the clamp to ROCm if you have gfx942 numbers — we could not measure it and did not want to change behaviour blind.

Fixes #441.

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[Leonccaa]

Nice measurements — the 19.3x on V100 is a big number and the "two warps can't
hide the latency" diagnosis matches what we see too.

One thing worth double-checking before this lands: on 1Cat main, the Qwen4Exp
dispatch in vllm/models/qwen4_exp/__init__.py selects by platform, not by
compute capability:

if current_platform.is_rocm():
    from .amd.model import ...
else:
    from .nvidia.model import ...

So on our 4x V100 (sm70, CUDA) it resolves to the nvidia/ tree — our runtime
logs show nvidia/ops/qsa.py:1600 ("Using SM70 grouped QSA Flash-V100 page4
prefill route"). We couldn't find a path where amd/ops/qsa.py gets imported
on CUDA; it's only reached via amd/qsa.py / amd/indexer_qsa.py under
amd/model.py. Possible we're missing something — could you check what your
box actually loads? (The CUDA branches inside amd/ops/qsa.py do make the
directory name misleading, so this is easy to trip over.)

If it turns out you're on the nvidia/ tree, note that
_qsa_sparse_launch_profile already has an sm70 retune with the same
reasoning:

if is_sm70 and block_n == 64:
    # Two warps serialize the D=256 tensor-core work on V100. Four warps
    # restore warp-level parallelism for split and non-split prefill.
    partial_warps = 4
    if base_programs >= 512:
        block_n = 32

It goes to 4 warps like yours, but narrows to BLOCK_N 32 rather than 16 — if
16 is genuinely better at 2048 rows, that's real headroom worth a PR against
the nvidia file.

For reference, roughly what we measure on 4x V100-32GB, Qwen3.8-Flash-Next
AWQ-g32, TP4/MTP0, FP16 activations, chunked prefill 8192, prefix caching off:

Cell	Prefill	Decode
C1 x 16K	~4.34k tok/s	~42 tok/s
C4 x 32K	~12.34k tok/s	~50 tok/s
C4 x 64K	~12.07k tok/s	~25 tok/s

Different geometry from yours (TP4 gives 6 query heads/rank vs your TP2xPP2,
and a 122B model rather than 180B), so not directly comparable — but we don't
see anything that looks like a 19x tile problem on this path, which is part of
why we suspect a dispatch difference.

On the shared-memory clamp: agreed it's the right shape of fix. FWIW at
HEAD_DIM 256 the widest current tile is
2*64*256*2 + 16*256*4 = 80 KiB, which fits Volta's 96 KiB but not Turing's
64 KiB — so the clamp matters for your RTX 8000 even if V100 is fine.

[yangzhuxinyzx]

Closing because this patch cannot affect the claimed CUDA V100/RTX8000 route in current main. Qwen4Exp dispatch selects amd/model.py only when current_platform.is_rocm(); CUDA SM70/SM75 loads nvidia/model.py. Every added tuning/clamp branch is additionally guarded with not current_platform.is_rocm(), so it is unreachable in the only production path that imports this file. Please resubmit the measured tile change against vllm/models/qwen4_exp/nvidia/ops/qsa.py with a route-hit trace and matched numerical/performance evidence.

[Peuqui]

You're right, and thank you for checking — this is a dispatch difference on our side, not on yours.

On 1Cat main, qwen4_exp/__init__.py selects purely by is_rocm(), so CUDA — including your V100s — loads the nvidia/ tree. Our machine runs a v100-skinny port of the Qwen4Exp tree on top of the 1.3.0 wheel, and that port routes compute_capability < 80 to the amd/ Triton tree because nvidia/ needs cute_dsl.skinny_gemm, which the wheel install doesn't have (the amd/ tree carries a no-op for it). Our harness (tools/qsa_bench.py) imports amd.ops.qsa, and our production logs show only the amd/ops/qsa route — so every number in #441 was measured against the amd/ops/qsa.py table, which upstream CUDA never executes. The "pre-Ampere takes the amd/ branch" note in #441 described our fork's dispatch, and I should have said so. Apologies for the noise.

What that means for this PR: as filed it patches a file that has no CUDA caller upstream, and the retune is CUDA-only, so it is effectively dead code on main. I'm converting it to a draft and will re-target the finding to nvidia/ops/qsa.py, where two things look real after reading _qsa_sparse_launch_profile:

1. Turing is not covered. The is_sm70 retune leaves sm75 on the GB300 table, and at HEAD_DIM 256 the widest tile needs 80 KiB — Turing grants 64 KiB, so on an RTX 8000 that tile cannot launch at all. A < 80 gate plus the opt-in shared-memory clamp would close that.
2. BLOCK_N 16 vs your 32 (≥512 programs) / 64 (32–511 programs) at 4 warps: our 19.3× was against the untuned GB300 profile, not against your sm70 retune, so it says nothing about that delta yet. I'll benchmark the nvidia/ file's profile against N16 on V100 and RTX 8000 at the 2048-row shape before claiming any headroom, and report the numbers here either way.

Your TP4 figures are useful calibration — ~12k tok/s prefill on 4× V100 is an order of magnitude above what our amd-tree path did before the retune, which fits the dispatch explanation exactly.

Would you prefer the re-targeted change as a force-push here or as a fresh PR against nvidia/ops/qsa.py?