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[LLVM][XTHeadVector] Implement intrinsics for vadc/vmadc/vsbc/vmsbc. (l…
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…lvm#52)

* [LLVM][XTHeadVector] Define intrinsics for vadc, etc.

* [LLVM][XTHeadVector] Define pseudos and pats for vadc/vsbc.

* [LLVM][XTHeadVector] Add test cases for vadc/vmadc.

* [LLVM][XTHeadVector] Add test cases for vsbc/vmsbc.

* [NFC][XTHeadVector] Update readme.
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@AinsleySnow
AinsleySnow authored Jan 15, 2024
1 parent 2524a2f commit e3938b3
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6 changes: 5 additions & 1 deletion README.md
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Expand Up @@ -30,7 +30,11 @@ Any feature not listed below but present in the specification should be consider
- (Done) `12.2. Vector Widening Integer Add/Subtract`
- (Done) `vwadd{u}.{vv,vx,wv,wx}`
- (Done) `vwsub{u}.{vv,vx,wv,wx}`

- (Done) `12.3. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions`
- (Done) `vadc.{vvm,vxm,vim}`
- (Done) `vmadc.{vvm,vxm,vim}`
- (Done) `vsbc.{vvm,vxm}`
- (Done) `vmsbc.{vvm,vxm}`
- (WIP) Clang intrinsics related to the `XTHeadVector` extension:
- (WIP) `6. Configuration-Setting and Utility`
- (Done) `6.1. Set vl and vtype`
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6 changes: 6 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
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Expand Up @@ -613,6 +613,12 @@ let TargetPrefix = "riscv" in {
defm th_vwsub : XVBinaryABX;
defm th_vwsubu_w : XVBinaryAAX;
defm th_vwsub_w : XVBinaryAAX;

// 12.3. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
defm th_vadc : RISCVBinaryWithV0;
defm th_vmadc_carry_in : RISCVBinaryMaskOutWithV0;
defm th_vsbc : RISCVBinaryWithV0;
defm th_vmsbc_borrow_in : RISCVBinaryMaskOutWithV0;
} // TargetPrefix = "riscv"

let TargetPrefix = "riscv" in {
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169 changes: 169 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
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Expand Up @@ -1723,6 +1723,72 @@ multiclass XVPseudoVWALU_WV_WX {
}
}

multiclass XVPseudoVCALU_VM_XM_IM {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);

defm "" : VPseudoTiedBinaryV_VM<m>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_XM<m>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_IM<m>,
Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
}
}

multiclass XVPseudoVCALUM_VM_XM_IM<string Constraint> {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);

defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
}
}

multiclass XVPseudoVCALU_VM_XM {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);

defm "" : VPseudoTiedBinaryV_VM<m>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
defm "" : VPseudoTiedBinaryV_XM<m>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
}
}

multiclass XVPseudoVCALUM_VM_XM<string Constraint> {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);

defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
}
}

//===----------------------------------------------------------------------===//
// Helpers to define the intrinsic patterns for the XTHeadVector extension.
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1903,6 +1969,72 @@ multiclass XVPatBinaryW_WX<string intrinsic, string instruction,
}
}

multiclass XVPatBinaryV_VM_TAIL<string intrinsic, string instruction> {
foreach vti = AllIntegerXVectors in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VVM",
vti.Vector,
vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>;
}

multiclass XVPatBinaryV_XM_TAIL<string intrinsic, string instruction> {
foreach vti = AllIntegerXVectors in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction,
"V"#vti.ScalarSuffix#"M",
vti.Vector,
vti.Vector, vti.Scalar, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.ScalarRegClass>;
}

multiclass XVPatBinaryV_IM_TAIL<string intrinsic, string instruction> {
foreach vti = AllIntegerXVectors in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VIM",
vti.Vector,
vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul,
vti.RegClass, vti.RegClass, simm5>;
}
multiclass XVPatBinaryV_VM<string intrinsic, string instruction,
bit CarryOut = 0,
list<VTypeInfo> vtilist = AllIntegerXVectors> {
foreach vti = vtilist in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
!if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul,
vti.RegClass, vti.RegClass>;
}

multiclass XVPatBinaryV_XM<string intrinsic, string instruction,
bit CarryOut = 0,
list<VTypeInfo> vtilist = AllIntegerXVectors> {
foreach vti = vtilist in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryIn<intrinsic, instruction,
"V"#vti.ScalarSuffix#"M",
!if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, vti.Scalar, vti.Mask,
vti.Log2SEW, vti.LMul,
vti.RegClass, vti.ScalarRegClass>;
}

multiclass XVPatBinaryV_IM<string intrinsic, string instruction,
bit CarryOut = 0> {
foreach vti = AllIntegerXVectors in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",
!if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul,
vti.RegClass, simm5>;
}

multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType = simm5>
: XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
Expand All @@ -1929,6 +2061,24 @@ multiclass XVPatBinaryW_WV_WX<string intrinsic, string instruction,
: XVPatBinaryW_WV<intrinsic, instruction, vtilist>,
XVPatBinaryW_WX<intrinsic, instruction, vtilist>;

multiclass XVPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
: XVPatBinaryV_VM_TAIL<intrinsic, instruction>,
XVPatBinaryV_XM_TAIL<intrinsic, instruction>,
XVPatBinaryV_IM_TAIL<intrinsic, instruction>;

multiclass XVPatBinaryM_VM_XM_IM<string intrinsic, string instruction>
: XVPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,
XVPatBinaryV_XM<intrinsic, instruction, CarryOut=1>,
XVPatBinaryV_IM<intrinsic, instruction, CarryOut=1>;

multiclass XVPatBinaryV_VM_XM<string intrinsic, string instruction>
: XVPatBinaryV_VM_TAIL<intrinsic, instruction>,
XVPatBinaryV_XM_TAIL<intrinsic, instruction>;

multiclass XVPatBinaryM_VM_XM<string intrinsic, string instruction>
: XVPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,
XVPatBinaryV_XM<intrinsic, instruction, CarryOut=1>;

//===----------------------------------------------------------------------===//
// 12.1. Vector Single-Width Saturating Add and Subtract
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2023,6 +2173,25 @@ let Predicates = [HasVendorXTHeadV] in {
defm : XVPatBinaryW_WV_WX<"int_riscv_th_vwsub_w", "PseudoTH_VWSUB", AllWidenableIntXVectors>;
}

//===----------------------------------------------------------------------===//
// 12.3. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXTHeadV] in {
defm PseudoTH_VADC : XVPseudoVCALU_VM_XM_IM;
defm PseudoTH_VMADC : XVPseudoVCALUM_VM_XM_IM<"@earlyclobber $rd">;

defm PseudoTH_VSBC : XVPseudoVCALU_VM_XM;
defm PseudoTH_VMSBC : XVPseudoVCALUM_VM_XM<"@earlyclobber $rd">;
} // Predicates = [HasVendorXTHeadV]

let Predicates = [HasVendorXTHeadV] in {
defm : XVPatBinaryV_VM_XM_IM<"int_riscv_th_vadc", "PseudoTH_VADC">;
defm : XVPatBinaryM_VM_XM_IM<"int_riscv_th_vmadc_carry_in", "PseudoTH_VMADC">;

defm : XVPatBinaryV_VM_XM<"int_riscv_th_vsbc", "PseudoTH_VSBC">;
defm : XVPatBinaryM_VM_XM<"int_riscv_th_vmsbc_borrow_in", "PseudoTH_VMSBC">;
} // Predicates = [HasVendorXTHeadV]

//===----------------------------------------------------------------------===//
// 12.14. Vector Integer Merge and Move Instructions
//===----------------------------------------------------------------------===//
Expand Down
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