[LLVM][XTHeadVector] Implement intrinsics for vmin{u}/vmax{u}. (llvm#61)

* [LLVM][XTHeadVector] Define intrinsic functions for vmin{u}/vmax{u}.

* [LLVM][XTHeadVector] Define pats and pseudos for vmin{u}/vmax{u}.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update README.

README.md

@@ -45,6 +45,7 @@ Any feature not listed below but present in the specification should be consider
       - (Done) `vsra.{vv,vx,vi}`
     - (Done) `12.6. Vector Narrowing Integer Right Shift Instructions`
     - (Done) `12.7 Vector Integer Comparison Instructions`
+    - (Done) `12.8. Vector Integer Min/Max Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -681,6 +681,12 @@ let TargetPrefix = "riscv" in {
   defm th_vmsgt : RISCVCompare;
   defm th_vmsge: RISCVCompare;
   defm th_vmsgeu: RISCVCompare;
+
+  // 12.8. Vector Integer Min/Max Instructions
+  defm th_vminu : XVBinaryAAX;
+  defm th_vmin : XVBinaryAAX;
+  defm th_vmaxu : XVBinaryAAX;
+  defm th_vmax : XVBinaryAAX;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2283,6 +2283,21 @@ multiclass XVPatCompare_VI<string intrinsic, string inst,
   }
 }
 
+multiclass XVPseudoVMINMAX_VV_VX {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVIMinMaxV_MX = !cast<SchedWrite>("WriteVIMinMaxV_" # mx);
+    defvar WriteVIMinMaxX_MX = !cast<SchedWrite>("WriteVIMinMaxX_" # mx);
+    defvar ReadVIMinMaxV_MX = !cast<SchedRead>("ReadVIMinMaxV_" # mx);
+    defvar ReadVIMinMaxX_MX = !cast<SchedRead>("ReadVIMinMaxX_" # mx);
+
+    defm "" : XVPseudoBinaryV_VV<m>,
+              Sched<[WriteVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VX<m>,
+              Sched<[WriteVIMinMaxX_MX, ReadVIMinMaxV_MX, ReadVIMinMaxX_MX, ReadVMask]>;
+  }
+}
+
 multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
                                  list<VTypeInfo> vtilist, Operand ImmType = simm5>
     : XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
@@ -2577,6 +2592,23 @@ let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatCompare_VI<"int_riscv_th_vmsltu", "PseudoTH_VMSLEU", simm5_plus1_nonzero>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 12.8. Vector Integer Min/Max Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VMINU : XVPseudoVMINMAX_VV_VX;
+  defm PseudoTH_VMIN  : XVPseudoVMINMAX_VV_VX;
+  defm PseudoTH_VMAXU : XVPseudoVMINMAX_VV_VX;
+  defm PseudoTH_VMAX  : XVPseudoVMINMAX_VV_VX;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vminu", "PseudoTH_VMINU", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vmin", "PseudoTH_VMIN", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vmaxu", "PseudoTH_VMAXU", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vmax", "PseudoTH_VMAX", AllIntegerXVectors>;
+}
+
 //===----------------------------------------------------------------------===//
 // 12.14. Vector Integer Merge and Move Instructions
 //===----------------------------------------------------------------------===//