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dts: bindings: usb: Specify fifo sizes in devicetree #99510

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dts: bindings: usb: Specify fifo sizes in devicetree #99510

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dts: bindings: usb: Specify fifo sizes in devicetree
tmon-nordic Nov 17, 2025
f3e1a59
drivers: usb: dwc2: Use fifo sizes from devicetree
tmon-nordic Nov 17, 2025
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349 changes: 125 additions & 224 deletions drivers/usb/udc/udc_dwc2.c
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5 changes: 1 addition & 4 deletions drivers/usb/udc/udc_dwc2.h
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Original file line number Diff line number Diff line change
Expand Up @@ -99,11 +99,7 @@ struct udc_dwc2_data {
uint16_t iso_out_rearm;
uint16_t ep_out_disable;
uint16_t ep_out_stall;
uint16_t txf_set;
uint16_t pending_tx_flush;
uint16_t dfifodepth;
uint16_t rxfifo_depth;
uint16_t max_txfifo_depth[16];
uint16_t sof_num;
/* Configuration flags */
unsigned int dynfifosizing : 1;
Expand Down Expand Up @@ -133,6 +129,7 @@ struct udc_dwc2_config {
size_t num_out_eps;
struct udc_ep_config *ep_cfg_in;
struct udc_ep_config *ep_cfg_out;
const uint16_t *const fifo_sizes;
/* Pointer to pin control configuration or NULL */
struct pinctrl_dev_config *const pcfg;
/* Pointer to vendor quirks or NULL */
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10 changes: 10 additions & 0 deletions dts/arm/intel_socfpga_std/socfpga.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -238,6 +238,11 @@
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x208ffc90>;
ghwcfg4 = <0xfe0f0020>;
/* 8064 locations with full flexibility */
g-rx-fifo-size = <608>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <512 512 512 512 512 512 512 512
512 512 512 512 512 512 256>;
status = "disabled";
};

Expand All @@ -251,6 +256,11 @@
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x208ffc90>;
ghwcfg4 = <0xfe0f0020>;
/* 8064 locations with full flexibility */
g-rx-fifo-size = <608>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <512 512 512 512 512 512 512 512
512 512 512 512 512 512 256>;
status = "okay";
};

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3 changes: 3 additions & 0 deletions dts/arm/syna/sr100.dtsi
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Expand Up @@ -192,6 +192,9 @@
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x02882054>; // 8 endpoints, dynamic sizing
ghwcfg4 = <0xe2003e20>; // 9 in endpoints, desc-DMA
g-rx-fifo-size = <576>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <512 512 256 256 256 256 256 256>;
status = "disabled";
};
};
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19 changes: 19 additions & 0 deletions dts/bindings/usb/snps,dwc2.yaml
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Expand Up @@ -51,3 +51,22 @@ properties:
description: |
Value of the GHWCFG4 register. It is used to determine available endpoint
types during driver pre-initialization.

g-rx-fifo-size:
type: int
required: true
description: |
Rx Data FIFO Depth. Must not exceed GRXFSIZ.RxFDep power-on value.
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@sylvioalves sylvioalves Dec 4, 2025

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Where RxFDep is used?

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@tmon-nordic tmon-nordic Dec 5, 2025 •
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The value provided in devicetree is validated in ASSERT. usb_dwc2_get_grxfsiz is returning GRXFSIZ.RxFDep value.

Devicetree is expected to contain proper value, and if it does not then ASSERT is the right way to notify user (developer who writes/modified devicetree snps,dwc2 entry).


g-np-tx-fifo-size:
type: int
required: true
description: |
IN Endpoint 0 FIFO Depth. Must not exceed GNPTXFSIZ.NPTXFDep power-on value.

g-tx-fifo-size:
type: array
required: true
description: |
IN Endpoint Transmit fifo depths. Values must not exceed their respective
DIEPTXFn.INEPnTxFDep power-on values.
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10 changes: 10 additions & 0 deletions dts/vendor/nordic/nrf54h20.dtsi
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Expand Up @@ -673,6 +673,16 @@
ghwcfg1 = <0xaa555000>;
ghwcfg2 = <0x22abfc72>;
ghwcfg4 = <0x1e10aa60>;
/* 3050 locations available, GRXFSIZ is 548,
* GNPTXFSIZ and DIEPTXFn are 512. The default
* values (upper bounds) sum up above the limit.
* Allow High-Bandwidth only on TxFIFO 1 and 2.
* Use maximum possible for RxFIFO and allocate
* everything remaining for TxFIFO 0.
*/
g-rx-fifo-size = <548>;
g-np-tx-fifo-size = <198>;
g-tx-fifo-size = <512 512 256 256 256 256 256>;
status = "disabled";
};

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5 changes: 5 additions & 0 deletions dts/vendor/nordic/nrf54lm20_a_b.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -252,6 +252,11 @@
ghwcfg1 = <0x0>;
ghwcfg2 = <0x22affc52>;
ghwcfg4 = <0x3e10aa60>;
/* 3040 locations with full flexibility */
g-rx-fifo-size = <592>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <512 256 256 256 256 256 256 256
16 16 16 16 16 16 16>;
status = "disabled";
};
};
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10 changes: 10 additions & 0 deletions dts/vendor/nordic/nrf9280.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -436,6 +436,16 @@
ghwcfg1 = <0xaa555000>;
ghwcfg2 = <0x22abfc72>;
ghwcfg4 = <0x1e10aa60>;
/* 3050 locations available, GRXFSIZ is 548,
* GNPTXFSIZ and DIEPTXFn are 512. The default
* values (upper bounds) sum up above the limit.
* Allow High-Bandwidth only on TxFIFO 1 and 2.
* Use maximum possible for RxFIFO and allocate
* everything remaining for TxFIFO 0.
*/
g-rx-fifo-size = <548>;
g-np-tx-fifo-size = <198>;
g-tx-fifo-size = <512 512 256 256 256 256 256>;
status = "disabled";
};

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3 changes: 3 additions & 0 deletions dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,9 @@
ghwcfg1 = <0x00000000>;
ghwcfg2 = <0x224dd930>;
ghwcfg4 = <0xd3f0a030>;
g-rx-fifo-size = <64>;
g-np-tx-fifo-size = <16>;
g-tx-fifo-size = <32 32 32 24>;
};

timer0: counter@6001f000 {
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