soc: xlnx: zynqmp: fix vectors and SRAM MPU region priority order #96689
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Place the 'vectors' region configuration behind the 'sram' and 'rom_region' configurations so that the MPU region for the vectors takes precedence over the 'sram' region due to higher region index = higher priority when resolving memory properties / permissions for overlapping regions. This is required for the vectors to work properly if the SRAM base address is also at 0x0. Fixes zephyrproject-rtos#96688. Signed-off-by: Immo Birnbaum <[email protected]>
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i faced the same issue, i also configured the vectors after 'sram' and 'rom' region when i'm verifying on ZCU102. Additionally, I noticed that the file soc/xlnx/zynqmp/arm_mpu_regions.c includes |
Please create the patch on top of this one. |
@venodela @michalsimek There's no such file in the cortex_a_r directory. <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h> is merely a helper file that converts the KCONFIG values specifying the current RAM and FLASH sizes to region size masks. It includes the already Cortex-variant-neutral header file <zephyr/arch/arm/mpu/arm_mpu.h> which eventually resolves to the variant-specific implementation at an even lower level (seems like the main difference between the M-MPU and the R-MPU is memory-based register access vs. CP15-based register access). I'd rather move this to a more generic place like zephyr/arch/arm/mpu if possible instead of placing a 100% identical clone of this header file in the cortex_a_r directory. The current placement is a historical debt of the fact that MPU support was there for Cortex-M first and for Cortex-R later and therefore some MPU related stuff wasn't named in a Cortex-agnostic way. |
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Place the 'vectors' region configuration behind the 'sram' and 'rom_region' configurations so that the MPU region for the vectors takes precedence over the 'sram' region due to higher region index = higher priority when resolving memory properties/permissions for overlapping regions. This is required for the vectors to work properly if the SRAM base address is also at 0x0.
Fixes #96688.