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Add driver for the Infineon S25H NOR flash#88446

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m-braunschweig wants to merge 5 commits intozephyrproject-rtos:mainfrom
siemens:mika/upstream/add-infineon-s25h-flash
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Add driver for the Infineon S25H NOR flash#88446
m-braunschweig wants to merge 5 commits intozephyrproject-rtos:mainfrom
siemens:mika/upstream/add-infineon-s25h-flash

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@m-braunschweig
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This driver adds support for the Infineon S25H NOR flash.

The changes were tested in combination of these changes and should only be merged after there is support for the AM243x launchpad and it's MSPI driver.

However I would still like some early review, especially since there now is a generic MSPI NOR driver (which wasn't merged when I started writing this driver) but it doesn't seem like it's possible to cleanly implement the disabling of the hybrid sector mode and the continous read feature might be a problem.

Add a infineon s25h mspi nor flash driver. This driver was tested on the
am243x-lp board in 1S-1S-1S mode.

The driver doesn't check the configuration for dummy cycles and assumes a
factory default configuration. It also changes, if needed, a non-volatile
configuration bit so the erase sectors are uniform. On startup the JEDEC id
is read and checked as basic communication test.

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Until now the Infineon S25H driver ran MSPI only in single IO mode. With
this change the driver now switches the IO mode to Quad SPI at the end of
the initialization for higher transfer rates

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The Infineon S25H driver requires the hybrid sectory architecture to be
disabled. For better readability this code has been moved into an own
function that is now called from the init function

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
To be able to address the full flash memory it's required to enter the 4
byte address mode. This is now done automatically during startup

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The s25h has a continous read mode that can be accidentially triggered, if
the address ends with a special bit pattern and the MSPI controller has a
high impedance state. To avoid this scenario it used to be forbidden to do
non-aligned reads.

This has now changed by reading the JEDEC id after a non-aligned read to
instead break the precondition for a continious read.

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
@swift-tk
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swift-tk commented Apr 11, 2025

Hi @m-braunschweig It might be best to include the driver in the same PR where MSPI driver support is #88487
Also it is desirable to add the drivers to examples/tests either under spi_nor or mspi for PR compile checks.

@m-braunschweig
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My idea was to keep the PRs small for faster review and since I do development/testing on the linked branch and then only cherry-pick the commits for the Pull Requests I think it should be fine

@m-braunschweig
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As suggested it's now part of #88487

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3 participants