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Merged
merged 4 commits into from
Feb 20, 2018
Merged

Enabling SPI ports on some nucleos #6172

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54cff2b
soc/stm32: Add DTS support for SPI port 2 on stm32f030 series
Feb 12, 2018
f83582f
drivers/pinmux: Provide common SPI1/SPI2 configuration on stm32f0
Feb 12, 2018
70b02bb
boards/arm: Enabling SPI ports on nucleo_f030r8
Feb 12, 2018
04b8505
boards/arm: Enabling SPI ports on nucleo_f103rb
Feb 12, 2018
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10 changes: 10 additions & 0 deletions boards/arm/nucleo_f030r8/Kconfig.defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -40,4 +40,14 @@ config I2C_2

endif

if SPI

config SPI_1
default y

config SPI_2
default y

endif

endif # BOARD_NUCLEO_F030R8
10 changes: 9 additions & 1 deletion boards/arm/nucleo_f030r8/nucleo_f030r8.dts
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Expand Up @@ -5,7 +5,7 @@
*/

/dts-v1/;
#include <st/stm32f030.dtsi>
#include <st/stm32f030X8.dtsi>

/ {
model = "STMicroelectronics STM32F030R8-NUCLEO board";
Expand Down Expand Up @@ -41,3 +41,11 @@
status = "ok";
clock-frequency = <I2C_BITRATE_FAST>;
};

&spi1 {
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@ydamigos ydamigos Feb 16, 2018

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You should also enable SPI_1 port in board's Kconfig.defconfig.

status = "ok";
};

&spi2 {
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@ydamigos ydamigos Feb 16, 2018

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Same here.

status = "ok";
};
12 changes: 12 additions & 0 deletions boards/arm/nucleo_f030r8/pinmux.c
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Expand Up @@ -31,6 +31,18 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PA11, STM32F0_PINMUX_FUNC_PA11_I2C2_SCL},
{STM32_PIN_PA12, STM32F0_PINMUX_FUNC_PA12_I2C2_SDA},
#endif /* CONFIG_I2C_2 */
#ifdef CONFIG_SPI_1
{STM32_PIN_PA4, STM32F0_PINMUX_FUNC_PA4_SPI1_NSS},
{STM32_PIN_PA5, STM32F0_PINMUX_FUNC_PA5_SPI1_SCK},
{STM32_PIN_PA6, STM32F0_PINMUX_FUNC_PA6_SPI1_MISO},
{STM32_PIN_PA7, STM32F0_PINMUX_FUNC_PA7_SPI1_MOSI},
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_SPI_2
{STM32_PIN_PB12, STM32F0_PINMUX_FUNC_PB12_SPI2_NSS},
{STM32_PIN_PB13, STM32F0_PINMUX_FUNC_PB13_SPI2_SCK},
{STM32_PIN_PB14, STM32F0_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F0_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif /* CONFIG_SPI_2 */
};

static int pinmux_stm32_init(struct device *port)
Expand Down
10 changes: 10 additions & 0 deletions boards/arm/nucleo_f103rb/Kconfig.defconfig
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Expand Up @@ -24,4 +24,14 @@ config PWM_STM32_1

endif # PWM

if SPI

config SPI_1
default y

config SPI_2
default y

endif

endif # BOARD_NUCLEO_F103RB
8 changes: 8 additions & 0 deletions boards/arm/nucleo_f103rb/nucleo_f103rb.dts
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Expand Up @@ -36,3 +36,11 @@
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
};

&spi1 {
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@ydamigos ydamigos Feb 16, 2018

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You should also enable SPI_1 port in board's Kconfig.defconfig.

status = "ok";
};

&spi2 {
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@ydamigos ydamigos Feb 16, 2018

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Same here.

status = "ok";
};
12 changes: 12 additions & 0 deletions boards/arm/nucleo_f103rb/pinmux.c
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Expand Up @@ -29,6 +29,18 @@ static const struct pin_config pinconf[] = {
#ifdef CONFIG_PWM_STM32_1
{STM32_PIN_PA8, STM32F1_PINMUX_FUNC_PA8_PWM1_CH1},
#endif /* CONFIG_PWM_STM32_1 */
#ifdef CONFIG_SPI_1
{STM32_PIN_PA4, STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS},
{STM32_PIN_PA5, STM32F1_PINMUX_FUNC_PA5_SPI1_MASTER_SCK},
{STM32_PIN_PA6, STM32F1_PINMUX_FUNC_PA6_SPI1_MASTER_MISO},
{STM32_PIN_PA7, STM32F1_PINMUX_FUNC_PA7_SPI1_MASTER_MOSI},
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_SPI_2
{STM32_PIN_PB12, STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS},
{STM32_PIN_PB13, STM32F1_PINMUX_FUNC_PB13_SPI2_MASTER_SCK},
{STM32_PIN_PB14, STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO},
{STM32_PIN_PB15, STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI},
#endif /* CONFIG_SPI_2 */
};

static int pinmux_stm32_init(struct device *port)
Expand Down
23 changes: 23 additions & 0 deletions drivers/pinmux/stm32/pinmux_stm32f0.h
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Expand Up @@ -51,18 +51,41 @@
#define STM32F0_PINMUX_FUNC_PB11_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_1 | STM32_OPENDRAIN_PULLUP)

#define STM32F0_PINMUX_FUNC_PA4_SPI1_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PA5_SPI1_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PA6_SPI1_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PA7_SPI1_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)

#define STM32F0_PINMUX_FUNC_PA15_SPI1_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB3_SPI1_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB4_SPI1_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB5_SPI1_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)

#define STM32F0_PINMUX_FUNC_PB12_SPI2_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB13_SPI2_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB14_SPI2_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB15_SPI2_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)

/* Available on STM32F030xC devices only. */
#define STM32F0_PINMUX_FUNC_PB9_SPI2_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PB10_SPI2_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PC2_SPI2_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32F0_PINMUX_FUNC_PC3_SPI2_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)

#endif /* _STM32F0_PINMUX_H_ */
21 changes: 21 additions & 0 deletions dts/arm/st/stm32f030X8.dtsi
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@@ -0,0 +1,21 @@
/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <st/stm32f030.dtsi>

/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};
21 changes: 21 additions & 0 deletions dts/arm/st/stm32f030Xc.dtsi
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@@ -0,0 +1,21 @@
/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <st/stm32f030.dtsi>

/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};