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Merged
merged 7 commits into from
Feb 20, 2018
Merged

dts: spi: add more dts nodes and fixup defines, convert boards to using dts #5883

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c3bf61b
dts: stm32: fix dts inclusion for stm32f405
Feb 9, 2018
dc12e53
dts: stm32: spi2 is not supported on all F4 SoCs
Feb 9, 2018
7919c6c
dts/arm/st: Fix SPI1 interrupt priority for STM32f0
ydamigos Feb 17, 2018
30de374
dts: stm32: add SPI nodes to dtsi files
Feb 9, 2018
0f62677
dts: stm32: add SPI nodes and give example for /delete-node/
Feb 14, 2018
ece105b
dts: spi: add remaining SPI fixup defines for STM32
Jan 28, 2018
50a5bd7
boards: arm: STM32 boards use DT to configure SPI
Jan 28, 2018
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5 changes: 5 additions & 0 deletions arch/arm/soc/st_stm32/stm32f0/dts.fixup
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Expand Up @@ -31,6 +31,11 @@
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0

#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0

#define FLASH_DEV_BASE_ADDRESS ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
#define FLASH_DEV_NAME ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL

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18 changes: 14 additions & 4 deletions arch/arm/soc/st_stm32/stm32f1/dts.fixup
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Expand Up @@ -28,9 +28,19 @@
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY

#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0

#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0

#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0

/* End of SoC Level DTS fixup file */
28 changes: 19 additions & 9 deletions arch/arm/soc/st_stm32/stm32f3/dts.fixup
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Expand Up @@ -30,15 +30,25 @@
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY

#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0

#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0

#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0

#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_FIFO_40003C00_IRQ_0

#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS
#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY
#define CONFIG_SPI_4_NAME ST_STM32_SPI_FIFO_40013C00_LABEL
#define CONFIG_SPI_4_IRQ ST_STM32_SPI_FIFO_40013C00_IRQ_0

#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
#define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL
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20 changes: 20 additions & 0 deletions arch/arm/soc/st_stm32/stm32f4/dts.fixup
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Expand Up @@ -60,6 +60,26 @@
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0

#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0

#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_40013400_BASE_ADDRESS
#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_40013400_IRQ_0_PRIORITY
#define CONFIG_SPI_4_NAME ST_STM32_SPI_40013400_LABEL
#define CONFIG_SPI_4_IRQ ST_STM32_SPI_40013400_IRQ_0

#define CONFIG_SPI_5_BASE_ADDRESS ST_STM32_SPI_40015000_BASE_ADDRESS
#define CONFIG_SPI_5_IRQ_PRI ST_STM32_SPI_40015000_IRQ_0_PRIORITY
#define CONFIG_SPI_5_NAME ST_STM32_SPI_40015000_LABEL
#define CONFIG_SPI_5_IRQ ST_STM32_SPI_40015000_IRQ_0

#define CONFIG_SPI_6_BASE_ADDRESS ST_STM32_SPI_40015400_BASE_ADDRESS
#define CONFIG_SPI_6_IRQ_PRI ST_STM32_SPI_40015400_IRQ_0_PRIORITY
#define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL
#define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0

#define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS_0
#define FLASH_DEV_NAME ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL

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5 changes: 5 additions & 0 deletions arch/arm/soc/st_stm32/stm32l4/dts.fixup
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Expand Up @@ -53,6 +53,11 @@
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0

#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0

#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL
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4 changes: 4 additions & 0 deletions boards/arm/96b_neonkey/96b_neonkey.dts
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Expand Up @@ -37,3 +37,7 @@
&i2c3 {
clock-frequency = <I2C_BITRATE_FAST>;
};

&spi1 {
status = "ok";
};
10 changes: 10 additions & 0 deletions boards/arm/96b_neonkey/Kconfig.defconfig
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Expand Up @@ -17,4 +17,14 @@ config UART_STM32_PORT_1

endif # UART_CONSOLE

if SPI

config SPI_1
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

endif # BOARD_96B_NEONKEY
13 changes: 13 additions & 0 deletions boards/arm/nucleo_f091rc/Kconfig.defconfig
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Expand Up @@ -27,4 +27,17 @@ config I2C_2

endif # I2C

if SPI

config SPI_1
default y

config SPI_2
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

endif # BOARD_NUCLEO_F091RC
8 changes: 8 additions & 0 deletions boards/arm/nucleo_f091rc/nucleo_f091rc.dts
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Expand Up @@ -40,3 +40,11 @@
status = "ok";
clock-frequency = <I2C_BITRATE_FAST>;
};

&spi1 {
status = "ok";
};

&spi2 {
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@ydamigos ydamigos Feb 10, 2018

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If we enable SPI2 port here, we should also enable it in Kconfig.defconfig.

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@dwagenk dwagenk Feb 10, 2018

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done

status = "ok";
};
10 changes: 10 additions & 0 deletions boards/arm/nucleo_f334r8/Kconfig.defconfig
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Expand Up @@ -17,4 +17,14 @@ config UART_STM32_PORT_2

endif # UART_CONSOLE

if SPI

config SPI_1
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

endif # BOARD_NUCLEO_F334R8
4 changes: 4 additions & 0 deletions boards/arm/nucleo_f334r8/nucleo_f334r8.dts
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Expand Up @@ -37,3 +37,7 @@
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
};

&spi1 {
status = "ok";
};
13 changes: 13 additions & 0 deletions boards/arm/nucleo_f401re/Kconfig.defconfig
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Expand Up @@ -24,6 +24,19 @@ config I2C_1

endif # I2C

if SPI

config SPI_1
default y

config SPI_2
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

if PWM

config PWM_STM32_2
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8 changes: 8 additions & 0 deletions boards/arm/nucleo_f401re/nucleo_f401re.dts
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clock-frequency = <I2C_BITRATE_FAST>;
};

&spi1 {
status = "ok";
};

&spi2 {
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@ydamigos ydamigos Feb 10, 2018

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If we enable SPI2 port here, we should also enable it in Kconfig.defconfig.

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@dwagenk dwagenk Feb 10, 2018

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done

status = "ok";
};

&flash0 {
partitions {
/*
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10 changes: 10 additions & 0 deletions boards/arm/nucleo_l432kc/Kconfig.defconfig
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Expand Up @@ -25,4 +25,14 @@ config PWM_STM32_2

endif # PWM

if SPI

config SPI_1
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

endif # BOARD_NUCLEO_L432KC
4 changes: 4 additions & 0 deletions boards/arm/nucleo_l432kc/nucleo_l432kc.dts
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pinctrl-names = "default";
status = "ok";
};

&spi1 {
status = "ok";
};
10 changes: 10 additions & 0 deletions boards/arm/nucleo_l476rg/Kconfig.defconfig
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Expand Up @@ -18,6 +18,16 @@ config UART_STM32_PORT_2

endif # UART_CONSOLE

if SPI

config SPI_1
default y

config SPI_STM32_INTERRUPT
default y

endif # SPI

if PWM

config PWM_STM32_2
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4 changes: 4 additions & 0 deletions boards/arm/nucleo_l476rg/nucleo_l476rg.dts
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pinctrl-names = "default";
status = "ok";
};

&spi1 {
status = "ok";
};
2 changes: 1 addition & 1 deletion dts/arm/st/stm32f0.dtsi
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Expand Up @@ -109,7 +109,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
interrupts = <25 5>;
interrupts = <25 3>;
status = "disabled";
label = "SPI_1";
};
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14 changes: 14 additions & 0 deletions dts/arm/st/stm32f072.dtsi
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Expand Up @@ -5,3 +5,17 @@
*/

#include <st/stm32f0.dtsi>

/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};
14 changes: 14 additions & 0 deletions dts/arm/st/stm32f091.dtsi
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Expand Up @@ -5,3 +5,17 @@
*/

#include <st/stm32f0.dtsi>

/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};
17 changes: 17 additions & 0 deletions dts/arm/st/stm32f103Xb.dtsi
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*/

#include <st/stm32f1.dtsi>

/ {
soc {
/* spi2 is present on all STM32F103xB SoCs except
* STM32F103TB. Delete node in stm32f103tb.dtsi.
*/
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
};
};
13 changes: 13 additions & 0 deletions dts/arm/st/stm32f103Xe.dtsi
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*/

#include <st/stm32f103Xb.dtsi>

/ {
soc {
spi3: spi@40003C00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003C00 0x400>;
interrupts = <51 5>;
status = "disabled";
};
};
};
20 changes: 20 additions & 0 deletions dts/arm/st/stm32f373.dtsi
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status = "disabled";
label= "I2C_2";
};

spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};

spi3: spi@40003C00 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003C00 0x400>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
};
};
10 changes: 0 additions & 10 deletions dts/arm/st/stm32f4.dtsi
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Expand Up @@ -135,16 +135,6 @@
status = "disabled";
label = "SPI_1";
};

spi2: spi@40003800 {
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all stm32f4 boards supported now by Zephyr have a SPI2 port. We could leave it as it is for now

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@dwagenk dwagenk Feb 10, 2018 •
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I moved SPI2 to stm32f401.dtsi, which is included directly or through other includes by every stm32f4 board that is supported by Zephyr right now.
Following the principle from previous discussion on this PR

dts representation should be faithful to each SoC

So I'd rather move it now, then have to do it later, when new SoCs are introduced

compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
};
};

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