drivers: reset: gd32: add initial support

drivers/adc/adc_gd32.c

@@ -9,6 +9,7 @@
 #include <errno.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/devicetree.h>
 
 #include <gd32_adc.h>
@@ -101,6 +102,7 @@ struct adc_gd32_config {
 #ifdef CONFIG_SOC_SERIES_GD32F3X0
 	uint32_t rcu_clock_source;
 #endif
+	struct reset_dt_spec reset;
 	uint8_t channels;
 	const struct pinctrl_dev_config *pcfg;
 	uint8_t irq_num;
@@ -348,6 +350,8 @@ static int adc_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
 
+	(void)reset_line_toggle_dt(&cfg->reset);
+
 #if defined(CONFIG_SOC_SERIES_GD32F403) || \
 	defined(CONFIG_SOC_SERIES_GD32VF103) || \
 	defined(CONFIG_SOC_SERIES_GD32F3X0)
@@ -446,6 +450,7 @@ static void adc_gd32_global_irq_cfg(void)
 	const static struct adc_gd32_config adc_gd32_config_##n = {				\
 		.reg = DT_INST_REG_ADDR(n),							\
 		.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock),				\
+		.reset = RESET_DT_SPEC_INST_GET(n),						\
 		.channels = DT_INST_PROP(n, channels),						\
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),					\
 		.irq_num = DT_INST_IRQN(n),							\

drivers/dac/dac_gd32.c

@@ -8,6 +8,7 @@
 
 #include <errno.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/drivers/dac.h>
 
 #include <gd32_dac.h>
@@ -29,6 +30,7 @@ LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL);
 struct dac_gd32_config {
 	uint32_t reg;
 	uint32_t rcu_periph_clock;
+	struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pcfg;
 	uint32_t num_channels;
 	uint32_t reset_val;
@@ -149,6 +151,8 @@ static int dac_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
 
+	(void)reset_line_toggle_dt(&cfg->reset);
+
 	return 0;
 }
 
@@ -159,6 +163,7 @@ static struct dac_gd32_data dac_gd32_data_0;
 static const struct dac_gd32_config dac_gd32_cfg_0 = {
 	.reg = DT_INST_REG_ADDR(0),
 	.rcu_periph_clock = DT_INST_PROP(0, rcu_periph_clock),
+	.reset = RESET_DT_SPEC_INST_GET(0),
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 	.num_channels = DT_INST_PROP(0, num_channels),
 	.reset_val = DT_INST_PROP(0, reset_val),

drivers/dma/dma_gd32.c

@@ -8,6 +8,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/logging/log.h>
 
 #include <gd32_dma.h>
@@ -54,6 +55,9 @@ struct dma_gd32_config {
 	uint32_t reg;
 	uint32_t channels;
 	uint32_t rcu_periph_clock;
+#ifdef CONFIG_SOC_SERIES_GD32F4XX
+	struct reset_dt_spec reset;
+#endif
 	void (*irq_configure)(void);
 };
 
@@ -586,6 +590,10 @@ static int dma_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
 
+#ifdef CONFIG_SOC_SERIES_GD32F4XX
+	(void)reset_line_toggle_dt(&cfg->reset);
+#endif
+
 	for (uint32_t i = 0; i < cfg->channels; i++) {
 		gd32_dma_interrupt_disable(cfg->reg, i,
 			   DMA_CHXCTL_FTFIE | GD32_DMA_INTERRUPT_ERRORS);
@@ -654,6 +662,8 @@ static const struct dma_driver_api dma_gd32_driver_api = {
 	static const struct dma_gd32_config dma_gd32##inst##_config = {        \
 		.reg = DT_INST_REG_ADDR(inst),                                 \
 		.rcu_periph_clock = DT_INST_PROP(inst, rcu_periph_clock),      \
+		IF_ENABLED(CONFIG_SOC_SERIES_GD32F4XX,                         \
+			   (.reset = RESET_DT_SPEC_INST_GET(inst),))           \
 		.channels = DT_INST_PROP(inst, dma_channels),                  \
 		.irq_configure = dma_gd32##inst##_irq_configure,               \
 	};                                                                     \

drivers/gpio/gpio_gd32.c

@@ -8,6 +8,7 @@
 
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/interrupt_controller/gd32_exti.h>
+#include <zephyr/drivers/reset.h>
 
 #include <gd32_gpio.h>
 #include <gd32_rcu.h>
@@ -44,6 +45,7 @@ struct gpio_gd32_config {
 	struct gpio_driver_config common;
 	uint32_t reg;
 	uint32_t rcu_periph_clock;
+	struct reset_dt_spec reset;
 };
 
 struct gpio_gd32_data {
@@ -346,6 +348,8 @@ static int gpio_gd32_init(const struct device *port)
 
 	rcu_periph_clock_enable(config->rcu_periph_clock);
 
+	(void)reset_line_toggle_dt(&config->reset);
+
 #ifdef CONFIG_GD32_HAS_AF_PINMUX
 	/* enable access to SYSCFG_EXTISSn registers */
 	rcu_periph_clock_enable(DT_PROP(SYSCFG_NODE, rcu_periph_clock));
@@ -364,6 +368,7 @@ static int gpio_gd32_init(const struct device *port)
 		},							       \
 		.reg = DT_INST_REG_ADDR(n),				       \
 		.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock),	       \
+		.reset = RESET_DT_SPEC_INST_GET(n),			       \
 	};								       \
 									       \
 	static struct gpio_gd32_data gpio_gd32_data##n;			       \

drivers/i2c/i2c_gd32.c

@@ -10,6 +10,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/drivers/i2c.h>
 
 #include <gd32_i2c.h>
@@ -33,6 +34,7 @@ struct i2c_gd32_config {
 	uint32_t reg;
 	uint32_t bitrate;
 	uint32_t rcu_periph_clock;
+	struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pcfg;
 	void (*irq_cfg_func)(void);
 };
@@ -663,6 +665,8 @@ static int i2c_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
 
+	(void)reset_line_toggle_dt(&cfg->reset);
+
 	cfg->irq_cfg_func();
 
 	bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
@@ -695,6 +699,7 @@ static int i2c_gd32_init(const struct device *dev)
 		.reg = DT_INST_REG_ADDR(inst),					\
 		.bitrate = DT_INST_PROP(inst, clock_frequency),			\
 		.rcu_periph_clock = DT_INST_PROP(inst, rcu_periph_clock),	\
+		.reset = RESET_DT_SPEC_INST_GET(inst),				\
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),			\
 		.irq_cfg_func = i2c_gd32_irq_cfg_func_##inst,			\
 	};									\

drivers/pwm/pwm_gd32.c

@@ -10,6 +10,7 @@
 
 #include <zephyr/drivers/pwm.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/sys/util_macro.h>
 
 #include <gd32_rcu.h>
@@ -39,8 +40,8 @@ struct pwm_gd32_config {
 	uint16_t prescaler;
 	/** RCU peripheral clock. */
 	uint32_t rcu_periph_clock;
-	/** RCU peripheral reset. */
-	uint32_t rcu_periph_reset;
+	/** Reset. */
+	struct reset_dt_spec reset;
 	/** pinctrl configurations. */
 	const struct pinctrl_dev_config *pcfg;
 };
@@ -234,9 +235,7 @@ static int pwm_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(config->rcu_periph_clock);
 
-	/* reset timer to its default state */
-	rcu_periph_reset_enable(config->rcu_periph_reset);
-	rcu_periph_reset_disable(config->rcu_periph_reset);
+	(void)reset_line_toggle_dt(&config->reset);
 
 	/* apply pin configuration */
 	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
@@ -272,8 +271,7 @@ static int pwm_gd32_init(const struct device *dev)
 		.reg = DT_REG_ADDR(DT_INST_PARENT(i)),			       \
 		.rcu_periph_clock = DT_PROP(DT_INST_PARENT(i),		       \
 					    rcu_periph_clock),		       \
-		.rcu_periph_reset = DT_PROP(DT_INST_PARENT(i),		       \
-					    rcu_periph_reset),		       \
+		.reset = RESET_DT_SPEC_GET(DT_INST_PARENT(i)),		       \
 		.prescaler = DT_PROP(DT_INST_PARENT(i), prescaler),	       \
 		.channels = DT_PROP(DT_INST_PARENT(i), channels),	       \
 		.is_32bit = DT_PROP(DT_INST_PARENT(i), is_32bit),	       \

drivers/reset/CMakeLists.txt

@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_RESET_GD32 reset_gd32.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_RPI_PICO reset_rpi_pico.c)

drivers/reset/Kconfig

@@ -28,5 +28,6 @@ config RESET_INIT_PRIORITY
 comment "Reset Controller Drivers"
 
 rsource "Kconfig.rpi_pico"
+rsource "Kconfig.gd32"
 
 endif # RESET

drivers/reset/Kconfig.gd32

@@ -0,0 +1,7 @@
+# Copyright (c) 2022 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config RESET_GD32
+	bool "GD32 Reset Controller Driver"
+	default y
+	depends on DT_HAS_GD_GD32_RCTL_ENABLED

drivers/reset/reset_gd32.c

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2022 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT gd_gd32_rctl
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/reset.h>
+
+/** RCU offset (from id field) */
+#define GD32_RESET_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
+/** RCU configuration bit (from id field) */
+#define GD32_RESET_ID_BIT(id)	 ((id) & 0x1FU)
+
+struct reset_gd32_config {
+	uint32_t base;
+};
+
+static int reset_gd32_status(const struct device *dev, uint32_t id,
+			     uint8_t *status)
+{
+	const struct reset_gd32_config *config = dev->config;
+
+	*status = !!sys_test_bit(config->base + GD32_RESET_ID_OFFSET(id),
+				 GD32_RESET_ID_BIT(id));
+
+	return 0;
+}
+
+static int reset_gd32_line_assert(const struct device *dev, uint32_t id)
+{
+	const struct reset_gd32_config *config = dev->config;
+
+	sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id),
+		    GD32_RESET_ID_BIT(id));
+
+	return 0;
+}
+
+static int reset_gd32_line_deassert(const struct device *dev, uint32_t id)
+{
+	const struct reset_gd32_config *config = dev->config;
+
+	sys_clear_bit(config->base + GD32_RESET_ID_OFFSET(id),
+		      GD32_RESET_ID_BIT(id));
+
+	return 0;
+}
+
+static int reset_gd32_line_toggle(const struct device *dev, uint32_t id)
+{
+	(void)reset_gd32_line_assert(dev, id);
+	(void)reset_gd32_line_deassert(dev, id);
+
+	return 0;
+}
+
+static const struct reset_driver_api reset_gd32_driver_api = {
+	.status = reset_gd32_status,
+	.line_assert = reset_gd32_line_assert,
+	.line_deassert = reset_gd32_line_deassert,
+	.line_toggle = reset_gd32_line_toggle,
+};
+
+static int reset_gd32_init(const struct device *dev)
+{
+	return 0;
+}
+
+static const struct reset_gd32_config config = {
+	.base = DT_REG_ADDR(DT_INST_PARENT(0)),
+};
+
+DEVICE_DT_INST_DEFINE(0, reset_gd32_init, NULL, NULL, &config, PRE_KERNEL_1,
+		      CONFIG_RESET_INIT_PRIORITY, &reset_gd32_driver_api);

drivers/serial/usart_gd32.c

@@ -7,6 +7,7 @@
 
 #include <errno.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/drivers/uart.h>
 
 #include <gd32_usart.h>
@@ -20,6 +21,7 @@
 struct gd32_usart_config {
 	uint32_t reg;
 	uint32_t rcu_periph_clock;
+	struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pcfg;
 	uint32_t parity;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
@@ -81,7 +83,9 @@ static int usart_gd32_init(const struct device *dev)
 	}
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
-	usart_deinit(cfg->reg);
+
+	(void)reset_line_toggle_dt(&cfg->reset);
+
 	usart_baudrate_set(cfg->reg, data->baud_rate);
 	usart_parity_config(cfg->reg, parity);
 	usart_word_length_set(cfg->reg, word_length);
@@ -318,6 +322,7 @@ static const struct uart_driver_api usart_gd32_driver_api = {
 	static const struct gd32_usart_config usart_gd32_config_##n = {		\
 		.reg = DT_INST_REG_ADDR(n),					\
 		.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock),		\
+		.reset = RESET_DT_SPEC_INST_GET(n),				\
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 		.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),	\
 		 GD32_USART_IRQ_HANDLER_FUNC_INIT(n)				\

drivers/spi/spi_gd32.c

@@ -9,6 +9,7 @@
 #include <errno.h>
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/reset.h>
 #include <zephyr/drivers/spi.h>
 
 #include <gd32_rcu.h>
@@ -41,6 +42,7 @@ LOG_MODULE_REGISTER(spi_gd32);
 struct spi_gd32_config {
 	uint32_t reg;
 	uint32_t rcu_periph_clock;
+	struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pcfg;
 #ifdef CONFIG_SPI_GD32_INTERRUPT
 	void (*irq_configure)();
@@ -339,6 +341,8 @@ int spi_gd32_init(const struct device *dev)
 
 	rcu_periph_clock_enable(cfg->rcu_periph_clock);
 
+	(void)reset_line_toggle_dt(&cfg->reset);
+
 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret) {
 		LOG_ERR("Failed to apply pinctrl state");
@@ -378,6 +382,7 @@ int spi_gd32_init(const struct device *dev)
 	static struct spi_gd32_config spi_gd32_config_##idx = {		       \
 		.reg = DT_INST_REG_ADDR(idx),				       \
 		.rcu_periph_clock = DT_INST_PROP(idx, rcu_periph_clock),       \
+		.reset = RESET_DT_SPEC_INST_GET(idx),			       \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),		       \
 		IF_ENABLED(CONFIG_SPI_GD32_INTERRUPT,			       \
 			   (.irq_configure = spi_gd32_irq_configure_##idx)) }; \