boards: Add support GigaDevice GD32V SoC #34970
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soburi
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Hi @soburi , very happy about you are PR to Zephyr with Nuclei SDK project, our team in Nuclei are also planning to provide zephyr integeration in future, using the Nuclei SDK project is a good choice. I also see you have made some changes to Nuclei SDK, any extra requrements to be maded to support Zephyr, maybe I can provide some help to see whether the changes can be placed in Nuclei SDK project directly. Thanks |
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some comments on the updated code.
Thanks for the cleanup, looking better.
GD32V SoC uses divided clock from core-clock for machine timer clock. Add config of clock divide factor to support GD32V. Signed-off-by: TOKITA Hiroshi <[email protected]>
GD32V processor core is used non-standard bitmask for mcause register. Add option to configure the bitmask to support GD32V. Signed-off-by: TOKITA Hiroshi <[email protected]>
Nuclei core has non-RISCV standard CSRs. Add a header file to suppor these CSRs. Signed-off-by: TOKITA Hiroshi <[email protected]>
Add configuration for GD32VF103 SoC. - Add compiler definition HXTAL_VALUE for compile GigaDevice's HAL. - Redefine gd32_cmsis_dir for source commonize. Signed-off-by: TOKITA Hiroshi <[email protected]>
Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <[email protected]>
SiPeed Longan Nano is a minimal development board based on GigaDevice's RISC-V processor. There are 2 board variations. longan_nano: GDGD32VF103CBT6 (128K Flash/32K SRAM) longan_nano_lite: GDGD32VF103C8T6 ( 64K Flash/20K SRAM) Signed-off-by: TOKITA Hiroshi <[email protected]>
Change the settings to support pinctrl on the GD32VF103. - Split soc/arm/gigadevice/common/pinctrl_soc.h and put it into include/dt-bindings. - Leave some definitions that can't handle with device tree compiler in pinctrl_soc.h. - Remove dependency to SOC_FAMILY_GD32 because always enabled it if GD32_HAS_AF(IO)_PINMAX was selected. Signed-off-by: TOKITA Hiroshi <[email protected]>
Add support for the ECLIC interrupt controller which is used with the Nuclei processor core. Signed-off-by: TOKITA Hiroshi <[email protected]>
Modifying configuration to enable with gd32vf103 - Add usart definition to devicetree. - Define USART_STAT as alias of USART_STAT0 if not defined it. - Enable USART if SOC_SERIES_RISCV_GIGADEVICE_GD32VF103. Signed-off-by: TOKITA Hiroshi <[email protected]>
Longan Nano boards pass the test that with calling coredump(). Signed-off-by: TOKITA Hiroshi <[email protected]>
When the case machine timer clock uses the divided system clock, k_cycle_get_32() can't measure accurately how many cycles elapsed. For example, use the value as timer clock obtained by dividing the system clock by 4. In this case, measuring a duration with k_cycle_get32() has up to 3 (4-1) cycles systematic error. To run this test, we need to insert an appropriate of nops with consideration for the errors. 'nop' can not repeat with for loop. Must insert as separated statement. But we don't have a convenient function such as BOOST_PP_REPEAT in C++. At this time, Implementing a generic test is a bit difficult. Skipping this test in the case. Signed-off-by: TOKITA Hiroshi <[email protected]>
Add soburi as gd32 platform collaborator. Signed-off-by: TOKITA Hiroshi <[email protected]>
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@tejlmand ping |
nandojve
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carlescufi
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This PR adds support for GigaDevice GD32V SoC and SiPeed Longan Nano board that is use the SoC.
(update 2021/11/26)
I found test_nop in tests/kernel/common/src/irq_offload.c is failed.
It seem to caused by CPU clock architecture, but bit difficult to workarounding. This PR skips the test.
(update 2021/11/08)hal_giadevice and minimal USART driver introduce with #38661.I modified this PR to only minimal change for support GD32V SoC.(I will add more drivers after this PR is approved.)At now, I found a twister test tests/subsys/cpp/libcxx/cpp.libcxx.newlib fails.The test case adds after this PR was issued.I'm working to solve it.Currently, the west module dependency points to https://github.com/soburi/hal_nuclei.SupportGPIO (with EXTI)UART (UART0 only, pins are fixed)WIPSupport pinctrl.Add SPI and other drivers.See #34971 for the HAL repo request.