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drivers: usb: udc: numaker: fix Control transfer issues#105824

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ccli8 wants to merge 2 commits intozephyrproject-rtos:mainfrom
ccli8:nvt_hsusbd_fix_ctrl_status_trigger
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drivers: usb: udc: numaker: fix Control transfer issues#105824
ccli8 wants to merge 2 commits intozephyrproject-rtos:mainfrom
ccli8:nvt_hsusbd_fix_ctrl_status_trigger

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@ccli8
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@ccli8 ccli8 commented Mar 19, 2026

For Nuvoton NuMaker SoC series, for UDC driver, this fixes some Control transfer issues:

  1. Remove unwanted Control Stage triggers for HSUSBD. The hardware handles Status OUT/IN automatically and needn't manual trigger.
  2. Remove misjudged Control OUT error check

ccli8 added 2 commits March 19, 2026 17:51
For HSUSBD, in Control transfer, the IN/OUT triggers for Statue
In/OUT stages are redundant because the hardware will handle them
via NAKCLR bit.

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Remove the error check because it may misjudge some right cases.
For example, for HSUSBD, in the case Setup-DataIn-StatusOut and
immediately following Setup-DataOut-StatusIn, next DataOut has
arrived but user buffer for OUT transfer may only ready for previous
StatusOut at this time.

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
@zephyrbot zephyrbot added the area: USB Universal Serial Bus label Mar 19, 2026
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@jfischer-no
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Needs to be reworked based on #103493

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@tmon-nordic tmon-nordic left a comment

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I think this PR can be closed, because I have fixed these issues (and few others) in rework-udc. I recommend that you look into the "host timeouts during control transfers" which was not covered with my fixes. My fixes only made the normal control transfers working (before rework-udc, the control transfer handling would hang after just a few quick control read followed by control write pairs).

/* Enable CEP interrupt */
base->CEPINTEN |= HSUSBD_CEPINTEN_TXPKIEN_Msk;
/* Enable CEP interrupt */
base->CEPINTEN |= HSUSBD_CEPINTEN_TXPKIEN_Msk;
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@tmon-nordic tmon-nordic Mar 20, 2026

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base->CEPINTEN |= and base->CEPINTEN &= ~ are not atomic. Both these essentially translate to:

  • read CEPINTEN value to a register
  • modify value in a register
  • write value to CEPINTEN

In the driver, the CEPINTEN is modified in both thread context and interrupt context. This leads to race conditions.

In rework-udc I have removed the dynamic CEPINTEN masking for everything except HSUSBD_CEPINTEN_RXPKIEN_Msk. When there is just one interrupt bit changed like this the race consequences are significantly lowered. I would recommend you to try to also eliminate the need for dynamically masking HSUSBD_CEPINTEN_RXPKIEN_Msk.

Comment on lines +1596 to +1602
if (len == 0) {
base->CEPCTL = HSUSBD_CEPCTL_ZEROLEN |
HSUSBD_CEPCTL_NAKCLR_Msk;
} else {
__ASSERT_NO_MSG(len <= ep_cur->mps);
base->CEPTXCNT = len;
}
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This is another problematic part that I fixed in rework-udc. Hopefully when len is zero, it is possible to just write 0 to base->CEPTXCNT. This eliminates the race related to accessing base->CEPCTL NAKCLR bit.

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ccli8 commented Mar 20, 2026

@tmon-nordic Many thanks for your rework and comment. I will do regression test and maybe re-raise related PR based on my test result.

@ccli8 ccli8 closed this Mar 20, 2026
@ccli8 ccli8 deleted the nvt_hsusbd_fix_ctrl_status_trigger branch March 20, 2026 07:52
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4 participants