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Stalearea: RISCVRISCV Architecture (32-bit & 64-bit)RISCV Architecture (32-bit & 64-bit)bugThe issue is a bug, or the PR is fixing a bugThe issue is a bug, or the PR is fixing a bugpriority: mediumMedium impact/importance bugMedium impact/importance bug
Description
In the current implementation of riscv _isr_wrapper(), z_riscv_switch will probably be called, then the context will switch to a normal thread, while the mret will not be excecuted to return from the interrupt mode. For MCUs with CLIC interrupt controller such as gd32vf103, mintstatus.mil will not be restored if mret is not executed. As a result, no other interrupts with the same level will be executed.
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Stalearea: RISCVRISCV Architecture (32-bit & 64-bit)RISCV Architecture (32-bit & 64-bit)bugThe issue is a bug, or the PR is fixing a bugThe issue is a bug, or the PR is fixing a bugpriority: mediumMedium impact/importance bugMedium impact/importance bug