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  • Yale University
  • New Haven, CT

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  1. riscv-cpu riscv-cpu Public

    RiscV CPU written by verilog, able to run implementation on FPGA board.

    Makefile 4

  2. RiscvSimulator RiscvSimulator Public

    RiscvSimulator with five stage pipeline

    C++

  3. MX-Compiler MX-Compiler Public

    A compiler from scratch for Mx (a c-and-java-like language)

    Java 4

  4. HappyTexing HappyTexing Public

    A collection of tools to boost the speed of latex coding.

    TeX 3