[Feature][MRV2] Default Model Runner V2 with compatibility fallbacks

[yjyang62]

What this PR does / why we need it?

This PR makes Model Runner V2 the default on Ascend when VLLM_USE_V2_MODEL_RUNNER is unset. The old architecture, feature, platform, and Triton whitelist is replaced by a blacklist in vllm_ascend/mrv2_utils.py.

When the env var is unset, a request uses V2 unless it matches one of these V1 fallbacks:

Models / platform

• Hy3-preview (HYV3*)
• Gemma4 (Gemma4*)
• 310P
• encoder-decoder (Whisper)
• pooling KV

Features

• LoRA
• VL encoder disaggregation (ec_transfer_config / encoder-only)
• VL encoder graph (compilation_config.cudagraph_mm_encoder)
• draft_window_size
• suffix speculative decoding
• ngram / ngram_gpu
• parallel_drafting
• dflash2 graph (DFlash2 without enforce_eager)

An explicit override still wins:

• VLLM_USE_V2_MODEL_RUNNER=0 forces V1
• VLLM_USE_V2_MODEL_RUNNER=1 forces V2

Upstream GPU / Triton V2 validation does not apply; Ascend owns runner selection.

Also drop stale VLLM_USE_V1 from the five DeepSeek-V3.2 nightlies so they take the default V2 path.

Does this PR introduce any user-facing change?

Yes. Unset VLLM_USE_V2_MODEL_RUNNER now defaults to Model Runner V2, except for the blacklist above. Keep V1 with VLLM_USE_V2_MODEL_RUNNER=0. Explicit 0 / 1 is unchanged.

How was this patch tested?

• Unit tests: tests/ut/test_mrv2_utils.py (default V2, blacklist fallback, env override)

• E2E / nightly: default V2 path, plus a few explicit VLLM_USE_V2_MODEL_RUNNER=0 pins

• CI: cpu-ut / e2e on this PR

• vLLM main: vllm-project/vllm@84030bb