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…park (vllm-project#16626) Stacked on vllm-project#16203. plus static `eagle3` / `mtp` / `dflash`. This PR only extends those two whitelists so more architectures and `dspark` can default to V2. Gating logic is otherwise unchanged: LoRA and dynamic speculative decoding (`num_speculative_tokens_per_batch_size`) still stay on V1, and `VLLM_USE_V2_MODEL_RUNNER` still overrides the whitelist. Default-V2 model architectures: - `Qwen3ForCausalLM` - `Qwen3MoeForCausalLM` - `MiniMaxM2ForCausalLM` - `DeepseekV3ForCausalLM` - `DeepseekV32ForCausalLM` - `GlmMoeDsaForCausalLM` - `DeepseekV4ForCausalLM` Default-V2 speculative methods: `eagle3` / `mtp` / `dflash` / `dspark`. Yes. The architectures above now default to Model Runner V2 when Triton is present, the platform is not 310P, and the feature whitelist is satisfied. Other models still default to V1. Explicit `VLLM_USE_V2_MODEL_RUNNER=0/1` is unchanged. - Unit tests updated: `tests/ut/test_mrv2_utils.py` (architecture parametrize, `dspark` on the feature whitelist) - CI: cpu-ut / e2e on this PR. - vLLM main: vllm-project/vllm@84030bb --------- Signed-off-by: yjyang62 <yangjinyang5@huawei.com> Signed-off-by: yjyang62 <yjyang62@users.noreply.github.com> Signed-off-by: Spicy-Stick <873805887@qq.com> Signed-off-by: ZhangwenTaoHW <zhangwentao101@huawei.com> Co-authored-by: yjyang62 <yjyang62@users.noreply.github.com> Co-authored-by: Spicy-Stick <873805887@qq.com> Co-authored-by: ZhangwenTaoHW <zhangwentao101@huawei.com> Co-authored-by: GDzhu01 <116337067+GDzhu01@users.noreply.github.com>
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What this PR does / why we need it?
Copies the complete change set from vllm-project#16626 without additional modifications.
Does this PR introduce any user-facing change?
Same as vllm-project#16626.
How was this patch tested?
No additional changes were made beyond the copied PR.