generated with new verison of svd2rust (#30)

xmc-rs · Nov 21, 2021 · eb91c9a · eb91c9a
1 parent 012ab19
commit eb91c9a
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diff --git a/Cargo.toml b/Cargo.toml
@@ -9,10 +9,10 @@ repository = "https://github.com/xmc-rs/xmc4100"
 documentation = "https://docs.rs/xmc4100"
 keywords = ["cortex-m", "xmc4x", "no_std", "svd2rust", "embedded"]
 categories = ["embedded", "no-std"]
+edition="2018"
 
 [dependencies]
-cortex-m = "0.7.0"
-bare-metal = "0.2.5"
+cortex-m = "0.7.3"
 vcell = "0.1.2"
 
 [dependencies.cortex-m-rt]

diff --git a/src/can.rs b/src/can.rs
@@ -2,130 +2,68 @@
 #[repr(C)]
 pub struct RegisterBlock {
     #[doc = "0x00 - CAN Clock Control Register"]
-    pub clc: CLC,
-    _reserved1: [u8; 4usize],
+    pub clc: crate::Reg<clc::CLC_SPEC>,
+    _reserved1: [u8; 0x04],
     #[doc = "0x08 - Module Identification Register"]
-    pub id: ID,
+    pub id: crate::Reg<id::ID_SPEC>,
     #[doc = "0x0c - CAN Fractional Divider Register"]
-    pub fdr: FDR,
-    _reserved3: [u8; 240usize],
-    #[doc = "0x100 - List Register"]
-    pub list: [LIST; 8],
-    _reserved4: [u8; 32usize],
-    #[doc = "0x140 - Message Pending Register"]
-    pub mspnd: [MSPND; 8],
-    _reserved5: [u8; 32usize],
-    #[doc = "0x180 - Message Index Register"]
-    pub msid: [MSID; 8],
-    _reserved6: [u8; 32usize],
+    pub fdr: crate::Reg<fdr::FDR_SPEC>,
+    _reserved3: [u8; 0xf0],
+    #[doc = "0x100..0x120 - List Register"]
+    pub list: [crate::Reg<list::LIST_SPEC>; 8],
+    _reserved4: [u8; 0x20],
+    #[doc = "0x140..0x160 - Message Pending Register"]
+    pub mspnd: [crate::Reg<mspnd::MSPND_SPEC>; 8],
+    _reserved5: [u8; 0x20],
+    #[doc = "0x180..0x1a0 - Message Index Register"]
+    pub msid: [crate::Reg<msid::MSID_SPEC>; 8],
+    _reserved6: [u8; 0x20],
     #[doc = "0x1c0 - Message Index Mask Register"]
-    pub msimask: MSIMASK,
+    pub msimask: crate::Reg<msimask::MSIMASK_SPEC>,
     #[doc = "0x1c4 - Panel Control Register"]
-    pub panctr: PANCTR,
+    pub panctr: crate::Reg<panctr::PANCTR_SPEC>,
     #[doc = "0x1c8 - Module Control Register"]
-    pub mcr: MCR,
+    pub mcr: crate::Reg<mcr::MCR_SPEC>,
     #[doc = "0x1cc - Module Interrupt Trigger Register"]
-    pub mitr: MITR,
+    pub mitr: crate::Reg<mitr::MITR_SPEC>,
 }
-#[doc = "CAN Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clc](clc) module"]
-pub type CLC = crate::Reg<u32, _CLC>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _CLC;
-#[doc = "`read()` method returns [clc::R](clc::R) reader structure"]
-impl crate::Readable for CLC {}
-#[doc = "`write(|w| ..)` method takes [clc::W](clc::W) writer structure"]
-impl crate::Writable for CLC {}
+#[doc = "CLC register accessor: an alias for `Reg<CLC_SPEC>`"]
+pub type CLC = crate::Reg<clc::CLC_SPEC>;
 #[doc = "CAN Clock Control Register"]
 pub mod clc;
-#[doc = "Module Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id](id) module"]
-pub type ID = crate::Reg<u32, _ID>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _ID;
-#[doc = "`read()` method returns [id::R](id::R) reader structure"]
-impl crate::Readable for ID {}
+#[doc = "ID register accessor: an alias for `Reg<ID_SPEC>`"]
+pub type ID = crate::Reg<id::ID_SPEC>;
 #[doc = "Module Identification Register"]
 pub mod id;
-#[doc = "CAN Fractional Divider Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fdr](fdr) module"]
-pub type FDR = crate::Reg<u32, _FDR>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _FDR;
-#[doc = "`read()` method returns [fdr::R](fdr::R) reader structure"]
-impl crate::Readable for FDR {}
-#[doc = "`write(|w| ..)` method takes [fdr::W](fdr::W) writer structure"]
-impl crate::Writable for FDR {}
+#[doc = "FDR register accessor: an alias for `Reg<FDR_SPEC>`"]
+pub type FDR = crate::Reg<fdr::FDR_SPEC>;
 #[doc = "CAN Fractional Divider Register"]
 pub mod fdr;
-#[doc = "List Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](list) module"]
-pub type LIST = crate::Reg<u32, _LIST>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _LIST;
-#[doc = "`read()` method returns [list::R](list::R) reader structure"]
-impl crate::Readable for LIST {}
+#[doc = "LIST register accessor: an alias for `Reg<LIST_SPEC>`"]
+pub type LIST = crate::Reg<list::LIST_SPEC>;
 #[doc = "List Register"]
 pub mod list;
-#[doc = "Message Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mspnd](mspnd) module"]
-pub type MSPND = crate::Reg<u32, _MSPND>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _MSPND;
-#[doc = "`read()` method returns [mspnd::R](mspnd::R) reader structure"]
-impl crate::Readable for MSPND {}
-#[doc = "`write(|w| ..)` method takes [mspnd::W](mspnd::W) writer structure"]
-impl crate::Writable for MSPND {}
+#[doc = "MSPND register accessor: an alias for `Reg<MSPND_SPEC>`"]
+pub type MSPND = crate::Reg<mspnd::MSPND_SPEC>;
 #[doc = "Message Pending Register"]
 pub mod mspnd;
-#[doc = "Message Index Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msid](msid) module"]
-pub type MSID = crate::Reg<u32, _MSID>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _MSID;
-#[doc = "`read()` method returns [msid::R](msid::R) reader structure"]
-impl crate::Readable for MSID {}
+#[doc = "MSID register accessor: an alias for `Reg<MSID_SPEC>`"]
+pub type MSID = crate::Reg<msid::MSID_SPEC>;
 #[doc = "Message Index Register"]
 pub mod msid;
-#[doc = "Message Index Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msimask](msimask) module"]
-pub type MSIMASK = crate::Reg<u32, _MSIMASK>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _MSIMASK;
-#[doc = "`read()` method returns [msimask::R](msimask::R) reader structure"]
-impl crate::Readable for MSIMASK {}
-#[doc = "`write(|w| ..)` method takes [msimask::W](msimask::W) writer structure"]
-impl crate::Writable for MSIMASK {}
+#[doc = "MSIMASK register accessor: an alias for `Reg<MSIMASK_SPEC>`"]
+pub type MSIMASK = crate::Reg<msimask::MSIMASK_SPEC>;
 #[doc = "Message Index Mask Register"]
 pub mod msimask;
-#[doc = "Panel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [panctr](panctr) module"]
-pub type PANCTR = crate::Reg<u32, _PANCTR>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _PANCTR;
-#[doc = "`read()` method returns [panctr::R](panctr::R) reader structure"]
-impl crate::Readable for PANCTR {}
-#[doc = "`write(|w| ..)` method takes [panctr::W](panctr::W) writer structure"]
-impl crate::Writable for PANCTR {}
+#[doc = "PANCTR register accessor: an alias for `Reg<PANCTR_SPEC>`"]
+pub type PANCTR = crate::Reg<panctr::PANCTR_SPEC>;
 #[doc = "Panel Control Register"]
 pub mod panctr;
-#[doc = "Module Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"]
-pub type MCR = crate::Reg<u32, _MCR>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _MCR;
-#[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"]
-impl crate::Readable for MCR {}
-#[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"]
-impl crate::Writable for MCR {}
+#[doc = "MCR register accessor: an alias for `Reg<MCR_SPEC>`"]
+pub type MCR = crate::Reg<mcr::MCR_SPEC>;
 #[doc = "Module Control Register"]
 pub mod mcr;
-#[doc = "Module Interrupt Trigger Register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mitr](mitr) module"]
-pub type MITR = crate::Reg<u32, _MITR>;
-#[allow(missing_docs)]
-#[doc(hidden)]
-pub struct _MITR;
-#[doc = "`write(|w| ..)` method takes [mitr::W](mitr::W) writer structure"]
-impl crate::Writable for MITR {}
+#[doc = "MITR register accessor: an alias for `Reg<MITR_SPEC>`"]
+pub type MITR = crate::Reg<mitr::MITR_SPEC>;
 #[doc = "Module Interrupt Trigger Register"]
 pub mod mitr;
diff --git a/src/can/clc.rs b/src/can/clc.rs
@@ -1,18 +1,54 @@
-#[doc = "Reader of register CLC"]
-pub type R = crate::R<u32, super::CLC>;
-#[doc = "Writer for register CLC"]
-pub type W = crate::W<u32, super::CLC>;
-#[doc = "Register CLC `reset()`'s with value 0x03"]
-impl crate::ResetValue for super::CLC {
-    type Type = u32;
-    #[inline(always)]
-    fn reset_value() -> Self::Type {
-        0x03
+#[doc = "Register `CLC` reader"]
+pub struct R(crate::R<CLC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CLC` writer"]
+pub struct W(crate::W<CLC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DISR` reader - Module Disable Request Bit"]
+pub struct DISR_R(crate::FieldReader<bool, bool>);
+impl DISR_R {
+    pub(crate) fn new(bits: bool) -> Self {
+        DISR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DISR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
     }
 }
-#[doc = "Reader of field `DISR`"]
-pub type DISR_R = crate::R<bool, bool>;
-#[doc = "Write proxy for field `DISR`"]
+#[doc = "Field `DISR` writer - Module Disable Request Bit"]
 pub struct DISR_W<'a> {
     w: &'a mut W,
 }
@@ -30,15 +66,39 @@ impl<'a> DISR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
-#[doc = "Reader of field `DISS`"]
-pub type DISS_R = crate::R<bool, bool>;
-#[doc = "Reader of field `EDIS`"]
-pub type EDIS_R = crate::R<bool, bool>;
-#[doc = "Write proxy for field `EDIS`"]
+#[doc = "Field `DISS` reader - Module Disable Status Bit"]
+pub struct DISS_R(crate::FieldReader<bool, bool>);
+impl DISS_R {
+    pub(crate) fn new(bits: bool) -> Self {
+        DISS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DISS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
+pub struct EDIS_R(crate::FieldReader<bool, bool>);
+impl EDIS_R {
+    pub(crate) fn new(bits: bool) -> Self {
+        EDIS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for EDIS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
 pub struct EDIS_W<'a> {
     w: &'a mut W,
 }
@@ -56,11 +116,11 @@ impl<'a> EDIS_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
         self.w
     }
 }
-#[doc = "Write proxy for field `SBWE`"]
+#[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
 pub struct SBWE_W<'a> {
     w: &'a mut W,
 }
@@ -78,7 +138,7 @@ impl<'a> SBWE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
         self.w
     }
 }
@@ -115,4 +175,30 @@ impl W {
     pub fn sbwe(&mut self) -> SBWE_W {
         SBWE_W { w: self }
     }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "CAN Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clc](index.html) module"]
+pub struct CLC_SPEC;
+impl crate::RegisterSpec for CLC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clc::R](R) reader structure"]
+impl crate::Readable for CLC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [clc::W](W) writer structure"]
+impl crate::Writable for CLC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLC to value 0x03"]
+impl crate::Resettable for CLC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x03
+    }
 }