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RTC Refactoring #51

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merged 5 commits into from
Oct 28, 2019
+39 −58
Merged

RTC Refactoring #51

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e465dd3
refactoring some initial methods
lucasbrendel Oct 28, 2019
7310c4d
Merge branch 'master' into rtc-refactor
lucasbrendel Oct 28, 2019
bd57a0e
removing unnecessary import for tests
lucasbrendel Oct 28, 2019
ec7f38e
refactored other methods
lucasbrendel Oct 28, 2019
a225c40
adding clippy task config for vscode
lucasbrendel Oct 28, 2019
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9 changes: 9 additions & 0 deletions .vscode/tasks.json
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,15 @@
"problemMatcher": [
"$rustc"
]
},
{
"label": "clippy",
"type": "process",
"command": "cargo",
"args": ["clippy", "--features", "xmc41xx"],
"problemMatcher": [
"$rustc"
]
}
]
}
88 changes: 30 additions & 58 deletions src/rtc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -178,43 +178,31 @@ impl RtcExt for Rtc {
pub struct Rtc {}

impl Rtc {
pub fn start(&self) {
let rtc = unsafe { &*RTC::ptr() };
let scu_gen = unsafe { &*SCU_GENERAL::ptr() };

while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
#[inline(always)]
fn wait_for_mirrsts(&self) {
while get_field!(SCU_GENERAL, mirrsts, rtc_ctr).bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
rtc.ctr.modify(|_, w| w.enb().set_bit());
}

pub fn stop(&self) {
let rtc = unsafe { &*RTC::ptr() };
let scu_gen = unsafe { &*SCU_GENERAL::ptr() };
pub fn start(&self) {
self.wait_for_mirrsts();
set!(RTC, ctr, enb);
}

while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
rtc.ctr.modify(|_, w| w.enb().clear_bit());
pub fn stop(&self) {
self.wait_for_mirrsts();
clear!(RTC, ctr, enb);
}

pub fn is_running(&self) -> bool {
let rtc = unsafe { &*RTC::ptr() };
let scu_gen = unsafe { &*SCU_GENERAL::ptr() };

while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
rtc.ctr.read().enb().bit_is_set()
self.wait_for_mirrsts();
get_field!(RTC, ctr, enb).bit_is_set()
}

pub fn set_prescaler(&self, prescaler: u16) {
let scu_gen = unsafe { &*SCU_GENERAL::ptr() };
while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
let rtc = unsafe { &*RTC::ptr() };
rtc.ctr.modify(|_, w| unsafe { w.div().bits(prescaler) });
self.wait_for_mirrsts();
set_field!(RTC, ctr, div, prescaler);
}

pub fn set_time(&self, time: Time) {
Expand All @@ -224,30 +212,25 @@ impl Rtc {
assert!(time.day < MAX_DAYS);
assert!(time.year < MAX_YEAR);

let scu_gen = unsafe { &*SCU_GENERAL::ptr() };
while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
let rtc = unsafe { &*RTC::ptr() };
self.wait_for_mirrsts();
let rtc = periph!(RTC);
// TODO: Not sure if this is fully correct. The C code does a single struct assignment.
rtc.tim0.modify(|_, w| unsafe {
rtc.tim0.write(|w| unsafe {
w.se().bits(time.second);
w.mi().bits(time.minute);
w.ho().bits(time.hour);
w.da().bits(time.day)
});
while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
rtc.tim1.modify(|_, w| unsafe {
self.wait_for_mirrsts();
rtc.tim1.write(|w| unsafe {
w.dawe().bits(time.weekday as u8);
w.mo().bits(time.month as u8);
w.ye().bits(time.year)
});
}

pub fn get_time(&self) -> Time {
let rtc = unsafe { &*RTC::ptr() };
let rtc = periph!(RTC);
Time {
second: rtc.tim0.read().se().bits(),
minute: rtc.tim0.read().mi().bits(),
Expand Down Expand Up @@ -280,29 +263,24 @@ impl Rtc {
assert!(time.day < MAX_DAYS);
assert!(time.year < MAX_YEAR);

let scu_gen = unsafe { &*SCU_GENERAL::ptr() };
while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
let rtc = unsafe { &*RTC::ptr() };
self.wait_for_mirrsts();
let rtc = periph!(RTC);
// TODO: Not sure if this is fully correct. The C code does a single struct assignment.
rtc.atim0.modify(|_, w| unsafe {
rtc.atim0.write(|w| unsafe {
w.ase().bits(time.second);
w.ami().bits(time.minute);
w.aho().bits(time.hour);
w.ada().bits(time.day)
});
while scu_gen.mirrsts.read().rtc_ctr().bit_is_clear() {
// Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending
}
rtc.atim1.modify(|_, w| unsafe {
self.wait_for_mirrsts();
rtc.atim1.write(|w| unsafe {
w.amo().bits(time.month as u8);
w.aye().bits(time.year)
});
}

pub fn get_alarm(&self) -> Time {
let rtc = unsafe { &*RTC::ptr() };
let rtc = periph!(RTC);
Time {
second: rtc.atim0.read().ase().bits(),
minute: rtc.atim0.read().ami().bits(),
Expand All @@ -329,24 +307,20 @@ impl Rtc {
}

pub fn get_event_status(&self) -> u32 {
let rtc = unsafe { &*RTC::ptr() };
rtc.stssr.read().bits()
get_reg!(RTC, stssr)
}

pub fn enable(&self) {
let scu = unsafe { &*SCU_POWER::ptr() };
let scu = periph!(SCU_POWER);
if scu.pwrstat.read().hiben().bit_is_clear() {
scu.pwrset.write(|w| w.hib().set_bit());
while scu.pwrstat.read().hiben().bit_is_clear() {}
}
}

pub fn is_enabled(&self) -> bool {
let scu_power = unsafe { &*SCU_POWER::ptr() };
let scu_reset = unsafe { &*SCU_RESET::ptr() };

scu_power.pwrstat.read().hiben().bit_is_set()
&& !scu_reset.rststat.read().hibrs().bit_is_set()
get_field!(SCU_POWER, pwrstat, hiben).bit_is_set()
&& !get_field!(SCU_RESET, rststat, hibrs).bit_is_set()
}

fn enable_event(&self) {
Expand All @@ -372,8 +346,6 @@ impl Rtc {

#[cfg(test)]
mod tests {
// Note this useful idiom: importing names from outer (for mod tests) scope.
use super::*;

#[test]
fn nothing() {
Expand Down