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@xia-stan
W. Hennig authored and xia-stan committed Feb 21, 2024
1 parent f173b83 commit e7c6e10
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Showing 11 changed files with 1,165 additions and 163 deletions.
6 changes: 5 additions & 1 deletion PixieNetDefs.h
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Expand Up @@ -33,8 +33,11 @@
* SUCH DAMAGE.
*----------------------------------------------------------------------*/

// generic
#define PI 3.14159265358979

// system constants
#define PS_CODE_VERSION 0x0230
#define PS_CODE_VERSION 0x0232
#define PN_BOARD_VERSION_12_250_A 0xA990
#define PN_BOARD_VERSION_12_250_B 0xA991
#define PN_BOARD_VERSION_12_250_B_PTP 0xA981
Expand Down Expand Up @@ -102,6 +105,7 @@
#define ACOUNTER_CLR 0x009
#define ARTC_CLR 0x00A
#define ABVAL 0x00B
#define ASPI 0x00C
#define CA_DAC 0x004

// block 1
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5 changes: 3 additions & 2 deletions README.md
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Expand Up @@ -22,10 +22,11 @@ software version 2.24.

| Firmware Type | Bit Res | Firmware ID | Firmware Files |
| --------------| ------- | ------------| -------------- |
| Standard | 12 | 0xA991_0231 | sd-bootfiles-pn-STD-2p31.zip |
| Standard | 14 | 0xA9A1_0231 | sd-bootfiles-pn-14B-2p31.zip |
| Standard | 12 | 0xA991_0232 | sd-bootfiles-pn-STD-2p32.zip |
| Standard | 14 | 0xA9A1_0232 | sd-bootfiles-pn-14B-2p32.zip |
| PSA | 12 | 0xA991_1231 | sd-bootfiles-pn-PSA-2p31.zip |


## File Name Conventions

| Component name | File Prefix | Description | Install & Update |
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108 changes: 93 additions & 15 deletions avgadc.c
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Expand Up @@ -71,7 +71,7 @@ int main(void) {
return rval;
}
const char *settings_file = "settings.ini";
rval = init_PixieNetFippiConfig_from_file( settings_file, 1, &fippiconfig ); // second override with user settings, do allow missing
rval = init_PixieNetFippiConfig_from_file( settings_file, 2, &fippiconfig ); // second override with user settings, do allow missing, no print
if( rval != 0 )
{
printf( "Failed to parse FPGA settings from %s, rval=%d\n", settings_file, rval );
Expand Down Expand Up @@ -122,42 +122,65 @@ int main(void) {
// **************** XIA code begins **********************


// 1. arm trigger
// 1a. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2. poll for capture to be finished
// 2a. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
printf("ADCTRIG = 0x%x \n", mval);
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x00F0) == 0) & (k< maxwait) ); // any of the 4 channels triggered and is done
if(k>=maxwait)
while ( ((mval & 0x0010) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
printf("Error: Waiting for trigger timed out \n");
return -1;
printf("Error: Waiting for trigger timed out, ch. 0 \n");
// return -1;
}



// 3. read 4K samples from ADC register
// 3a. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC0] & 0xFFFF;
k = mapped[AAVGADC1] & 0xFFFF;
k = mapped[AAVGADC2] & 0xFFFF;
k = mapped[AAVGADC3] & 0xFFFF;

if( (mval & 0x0010) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc0[k] = (int)floor((double)mapped[AAVGADC0] / scale[0] );
else
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc0[k] = (k & 0x0003) +0 ;
adc0[k] = (k & 0x0003) +0 ;




// 1b. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2b. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0020) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
printf("Error: Waiting for trigger timed out, ch. 1 \n");
// return -1;
}

// 3b. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC1] & 0xFFFF;

if( (mval & 0x0020) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
Expand All @@ -166,13 +189,68 @@ int main(void) {
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc1[k] = (k & 0x0003) +1 ;



// 1c. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2c. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0040) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
printf("Error: Waiting for trigger timed out, ch. 2 \n");
// return -1;
}

// 3c. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC2] & 0xFFFF;

if( (mval & 0x0040) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc2[k] = (int)floor((double)mapped[AAVGADC2] / scale[2] );
else
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc2[k] = (k & 0x0003) +2 ;



// 1d. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples


// 2d. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0080) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
printf("Error: Waiting for trigger timed out, ch. 3 \n");
// return -1;
}

// 3d. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC3] & 0xFFFF;

if( (mval & 0x0080) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc3[k] = (int)floor((double)mapped[AAVGADC3] / scale[3] );
Expand Down
108 changes: 93 additions & 15 deletions cgiavgtraces.c
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Original file line number Diff line number Diff line change
Expand Up @@ -122,42 +122,65 @@ int main(void) {

// **************** XIA code begins **********************

// 1. arm trigger
// 1a. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2. poll for capture to be finished
// 2a. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(10000);
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
// printf("ADCTRIG = 0x%x \n", mval);
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x00F0) == 0) & (k< maxwait) ); // any of the 4 channels triggered and is done
if(k>=maxwait)
while ( ((mval & 0x0010) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
printf("Error: Waiting for trigger timed out \n");
return -1;
printf("Error: Waiting for trigger timed out, ch. 0 \n");
// return -1;
}



// 3. read 4K samples from ADC register
// 3a. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC0] & 0xFFFF;
k = mapped[AAVGADC1] & 0xFFFF;
k = mapped[AAVGADC2] & 0xFFFF;
k = mapped[AAVGADC3] & 0xFFFF;

if( (mval & 0x0010) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc0[k] = (int)floor((double)mapped[AAVGADC0] / scale[0] );
else
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc0[k] = (k & 0x0003) +0 ;
adc0[k] = (k & 0x0003) +0 ;




// 1b. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2b. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0020) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
//printf("Error: Waiting for trigger timed out, ch. 1 \n");
// return -1;
}

// 3b. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC1] & 0xFFFF;

if( (mval & 0x0020) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
Expand All @@ -166,13 +189,68 @@ int main(void) {
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc1[k] = (k & 0x0003) +1 ;



// 1c. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples

// 2c. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0040) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
// printf("Error: Waiting for trigger timed out, ch. 2 \n");
// return -1;
}

// 3c. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC2] & 0xFFFF;

if( (mval & 0x0040) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc2[k] = (int)floor((double)mapped[AAVGADC2] / scale[2] );
else
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc2[k] = (k & 0x0003) +2 ;



// 1d. arm trigger
mapped[AOUTBLOCK] = OB_IOREG;
mapped[ACOUNTER_CLR] = 1; // any write to COUNTER_CLR arms the trigger for capturing averaged samples


// 2d. poll for capture to be finished
mapped[AOUTBLOCK] = OB_EVREG; // switch reads to event data block of addresses
k=0;
do {
usleep(1000);
k=k+1;
mval = mapped[AADCTRIG];
//printf("ADCTRIG = 0x%x \n", mval);
}
while ( ((mval & 0x0080) == 0) & (k< maxwait) ); // wait the estimated time, for this channel
if( (k>=maxwait) ) // not even one trigger found
{
// printf("Error: Waiting for trigger timed out, ch. 3 \n");
// return -1;
}

// 3d. read 4K samples from ADC register

// dummy reads for sampling update
k = mapped[AAVGADC3] & 0xFFFF;

if( (mval & 0x0080) >0) // read only traces that triggered
for( k = 0; k < NAVG_TRACE_SAMPLES; k ++ )
adc3[k] = (int)floor((double)mapped[AAVGADC3] / scale[3] );
Expand Down
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